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SN74AVC4T774: Level Shifter solution for triple SPI

Tamio Yokokura
Expert 3770 points
Part Number: SN74AVC4T774
Other Parts Discussed in Thread: SN74AUC34, 2N7001T

Logic support team

I designed the following circuit that used 2 pcs of SN74AVC5T774 as supporting 3 pcs of SPI peripherals.

If you have any concern, please let me know about that.

Thanks

Tamio

  • 0
    Guru 297680 points
    The four unused inputs of the second translator must not be open, and all DIR inputs can be hardcoded. And any signal that is not actively driven at all times (MISO, and maybe MOSI) needs a pull-up or pull-down.

    It would be simpler and cheaper to use a SN74AUC34 for shifting down (it has overvoltage-tolerant inputs) and a 2N7001T for shifting up.
  • 0 in reply to Clemens Ladisch
    TI__Expert 3770 points

    Thank you for your advice.

    Customer requires to eliminate the type of parts even if it become cost up.

    I updated my circuit based on your advice as follows.

     - Connect unused DIR, A and B to GND directly

     - Connect MISO and MOSI to VCCA or VCCB via a resister 

    Thanks

    Tamio

  • 0 in reply to Tamio Yokokura
    Guru 297680 points

    I am not aware of a device called "SN74AXC4T774".

    You do not need pull-up resistors on the high DIR inputs; CMOS inputs can be connected directly to VCC or GND. (These resistors would be useful only if you wanted to force a different voltage when debugging the board.)

    Unused outputs (A3/A4 on the second shifter) do not need to be grounded.

    When the OE signals are high, all the shifter outputs are high impedance. So if the controller is actually going to disable the shifters while the SPI peripherals are still powered up, all signals need pullups. (But the OEs were not mentioned in the first circuit; are the shifters actually disabled at any time?)

  • 0 in reply to Clemens Ladisch
    TI__Guru* 96977 points
    Hey Clemens,
    The AXC4T774 hasn't been released yet, but it's something we're working on -- planned for release later this year.