• State Resolved
  • Locked Locked
  • Replies 2 replies
  • Subscribers 19 subscribers
  • Views 412 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

SN74LVC1G125: detailed output architecture

Ue
Genius 17165 points
Part Number: SN74LVC1G125

Hi all

While looking at the SN74LVC1G125 Datasheet I come across comments in section 10.2.1 (copied below).

Can you elaborate on the implications ?

Can you provide a functional block diagram and a detailed description of the architecture of the output stage ?

Thank you for providing feedback

Ueli

----------------------------------

10.2.1 Design Requirements This device uses CMOS technology and has balanced output drive. Care should be taken to avoid bus contention because it can drive currents that would exceed maximum limits. The high drive will also create fast edges into light loads so routing and load conditions should be considered to prevent ringing.

  • 0
    TI__Guru* 97046 points

    Hi Ue,

    The statement you have quoted from the datasheet seems very direct to me.  What part of it is confusing to you?

    The output of a CMOS device typically has this architecture:

    There are other implementations, but they always include a pFET on the positive side to source current, and an nFET on the negative side to sink current.

  • 0 in reply to Emrys Maier
    TI__Genius 17165 points

    Hi Emrys

    Thank you for the quick reply.

    This is a question I get from a customer and your reply clarifies the output structure.

    Best regards

    Ueli