SN74HC595: SN74HC595DR if SRCLR pin is pull Low, why output waveform have one puls to high?

Lawrence He

Genius 3280 points

Part Number: SN74HC595

Dear,

we use SN74HC595DR, but we find, if power on and SRCLR pin was pull low, why output wavform have one puls? is normal?

measurement waveform as below chart:

schematic:

If any suggestion, Please advise me.

Thanks,

Best regards,

Lawrence.

over 6 years ago

0 Dylan Hubbard over 6 years ago

TI__Mastermind 45725 points

Hi Lawrence,

Could I get another scope shot that shows the output and the two clock signals as well as the clear signal? I believe I know what the problem is. Since the storage register stage are flip flops, there is no guarantee what the output will be so it could start up High(see below FAQ). You are clearing the shift register stage, but you may not be clocking that to the storage register until when the output signal goes low. This is why I wanted to see what the clock signals were doing.

e2e.ti.com/.../737715

0 Lawrence He over 6 years ago in reply to Dylan Hubbard

Genius 3280 points

Hi, Dylan

We catch two clock signals and output waveform, and we find If use Probe to connect or disconnect RCLK pin , it was can change output waveform.

Probe connect to RCLK , output pulse waveform was gone.

Probe disconnect to RCLK, output have one puls waveform.

so how to follow datasheet 9.4 function table

schematic as below file.

< removed due to confidentiality>

If any suggestion, Please advise me.

Thanks,

Best regards,

Lawrence.

0 Clemens Ladisch over 6 years ago in reply to Lawrence He

Guru 316640 points

See the FAQ linked by Dylan: [FAQ] What is the default output of a latched device? (Flip-Flop, latch, register)

SRCLR clears only the shift register. Before the first rising edge on RCLK, the values in the storage register (and thus the output pins) are undefined.

If you want the outputs to be low, you must generate a rising edge on RCLK.

0 Lawrence He over 6 years ago in reply to Clemens Ladisch

Genius 3280 points

Hi, Clemens Ladisch

Yes! we want output to be low, but we find power up to RCLK generate a rising edge at the same time output have one puls waveform.

is could avoid?

because this behavior affect next step device , will false action.

if any suggestion, Please advise me.

Thanks,

Best regards,

Lawrence.

0 Clemens Ladisch over 6 years ago in reply to Lawrence He

Guru 316640 points

To prevent the device from outputting unwanted values, initialize it with the OE pin high, and pull it low only after the first RCLK.

0 Lawrence He over 6 years ago in reply to Clemens Ladisch

Genius 3280 points

Hi, Clemens Ladisch

Thank you , we will try it.

have about at power up , SN74HC595DR input and output function table document, can share us?

if any, Please advise me.

Thanks,

Best regards,

Lawrence.

0 user5872838 over 6 years ago in reply to Clemens Ladisch

Prodigy 90 points

Hi, Clemens Ladisch：

Have any document about RCLK & OE# timing setting ?
If you have all signal timing setting's document is best.
Thanks

0 user5872838 over 6 years ago in reply to Clemens Ladisch

Prodigy 90 points

Have any document about RCLK & OE# timing setting ?
If you have all signal timing setting's document is best.

0 Clemens Ladisch over 6 years ago in reply to Lawrence He

Guru 316640 points

There is no other document; see the function table and the FAQ shown above.

0 Dylan Hubbard over 6 years ago in reply to Clemens Ladisch

TI__Mastermind 45725 points

Hi Lawrence,

A scope probe shouldn't affect anything when probing RCLK so I'm not sure what you are experiencing. I do see the output going low when you clock the RCLK pin shifting everything in the shift register into the storage register. The output pulse from when you disconnect the RCLK probe is the same amount of time as the time between the power on and the RCLK rising edge.

Utilizing the OE pin and pull-downs will be a good way to default the device outputs to Low before the RCLK can shift the cleared shift register into the output register. Timing specifications can be found in section 7.6 of the datasheet.

I'm removing the the linked schematic as it is confidential and I can't look at it unless I see proof of an NDA. Please refrain from posting anything confidential on this forum as it is public and anyone can see it.

0 Lawrence He over 6 years ago in reply to Clemens Ladisch

Genius 3280 points

Hi, Clemens Ladisch

about your reply :To prevent the device from outputting unwanted values, initialize it with the OE pin high, and pull it low only after the first RCLK.

after the first RCLK , when to OE pin to be low?

OE pin high to low, have min time or max time limit?

If any, Please advise me.

Thanks,

Best regards,

Lawrence.

0 Clemens Ladisch over 6 years ago in reply to Lawrence He

Guru 316640 points

To be safe, add the maximum times of t_pd and t_en.
(If the load capcitance is lower than 50 pF, the times will also be lower.)

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SN74HC595: SN74HC595DR if SRCLR pin is pull Low, why output waveform have one puls to high?