Because of the holidays, TI E2E™ design support forum responses will be delayed from Dec. 25 through Jan. 2. Thank you for your patience.

  • State TI Thinks Resolved
  • Locked Locked
  • Replies 4 replies
  • Answers 2 answers
  • Subscribers 19 subscribers
  • Views 559 views
  • Users 0 members are here
Support feedback
Options
Options
Similar topics

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

TXB0108: Can't read Flash_6MBPS_6MHz Clock

user5707026
Genius 3145 points
Part Number: TXB0108
Other Parts Discussed in Thread: SN74AVC4T774

Hi 

Hello, this is a schematic. Among them, 1.5V to 3.3V has not been working. 3.3V to 3.3V can sometimes work normally, sometimes not. When it can't work, it always outputs 3MHz clock and can't read FLASH. The attached picture is the timing diagram of the SPI mode for the FPGA configuration FLASH. I hope you can answer why 1.5V to 3.3V can't work. The FPGA bank voltage is 1.5V or 3.3V related configuration I changed. thank you!

Figure 1. FPGA configuration FLASH timing diagram

Figure 2. Can't read Flash_6MBPS_6MHz Clock

Figure 3. This can work_Sometimes Can't read Flash_6MBPS_6MHz Clock

  • 0
    Guru 283370 points

    TXB translators are designed to be connected directly to CMOS I/Os, ideally without any other componets. But the schematic shows series and pull-up resistors; it's likely that those ruin your signal voltages. See section 8.3.5 of the datasheet, and Effects of External Pullup and Pulldown Resistors on TXS and TXB Devices (SCEA054).

    Try using pull-up resistors with more than 50 kΩ, and reducing the series resistors.

  • 0 in reply to Clemens Ladisch
    TI__Guru 58670 points
    Thanks for the reply, Clemens.
    Elsa,

    I do not see any translation requirements based on the supply voltages except for the first one.
    You could remove or increase the value of the pullup resistors and it shouldnt affect the signal integrity of the push pull signals of the SPI.
    Else, you could consider using the SN74AVC4T774 buffered voltage level translator.
  • 0 in reply to Clemens Ladisch
    Genius 3145 points

    Hi

    In my schematic diagram, the pull-up resistance is not added, but the series resistance is added! Just now I tried to change the series resistance directly to 0 ohm resistance, the same phenomenon.           

    Are there any QPI mode conversion chips available for the chip models? Most FLASH now supports SPI and QPI. Spi downloads slowly.

  • 0 in reply to user5707026
    Guru 283370 points
    If those SIO signals are bidirectional, and if it is not possible to control the signal direction from the FPGA, then it is not possible to use a direction-controlled translator like the SN74AVCxTxxx.

    In theory, the TXB should work. What is the distance between the FPGA and the flash? Please show the signals when captured with an oscilloscope.