This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

TXS0102: Some questions

Part Number: TXS0102

Hi Sirs,

Sorry to bother you.

We have some questions for I2C level shifter TXS0102, Could you please help to take a look?


1. Is there any CL (load capacitance) limitation for its I/O pin?
2 Could you advise the suggested quantity of I2C slave devices which are paralleled together for its same I/O bus?

Thanks!!

  • Section 4 of the application report A Guide to Voltage Translation With TXS-Type Translators (SCEA044) says:

    There is a tradeoff between achieving a maximum data rate and driving heavy capacitive loads simultaneously. With heavy capacitive loads, the one-shot can time-out before the signal is driven fully to the positive rail. In this scenario, only the pull-up resistors will pull the line high in accordance with its RC time-constant determined by the resistive and capacitive loadings. It is best to avoid this condition by driving capacitive loads less than 70pF when maximum data rate are desired. With capacitive loading >70pF, the TXS-type devices will still successfully operate at lower data rates.

    Please note that maximum data rate that the TXS can achieve with 70 pF is 2 Mbit/s. The I²C specification limits fast-mode speed to 400 bit/s, with a maximum bus capacitance of 400 pF; this should work fine.