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SN74LVC1G14-Q1: clipped sine wave (0.8Vpp) to CMOS level transfer

Shinji Tsuji
Genius 13118 points
Part Number: SN74LVC1G14-Q1
Other Parts Discussed in Thread: TLV3201-Q1, SN74AUP1T34-Q1, TLV3201, TLV3501, TLV3501A-Q1, SN74LVC1G04-Q1

Hi team,

I would like to translate 0.8Vpp TCXO output clock to 1.8V CMOS level input for TDA2x.

TCXO output is 0.8Vpp clipped sine wave and DC cut by series capacitor. 

I wonder Vin tolerance of SN74LVC1G14-Q1 is marginal to receive 0.8Vpp.

Could you recommend any good solution for this application?

  • 0
    TI__Guru* 96802 points
    Hello Tsuji-san,
    All logic Schmitt-trigger input devices have a pretty wide input threshold range. The 1G14 you listed has a possible range of 0.39V to 1.56V at 1.65V supply, which is larger than the signal size you have -- ie we can't guarantee the device would switch.

    I would recommend using a comparator.
  • 0 in reply to Emrys Maier
    TI__Genius 13118 points

    Thank you very much.

    Could you advise if this comparator TLV3201-Q1 can be used for 20MHz clock?

    regards,

  • 0 in reply to Shinji Tsuji
    Guru 277220 points
    At 20 MHz, the signal edges are 50 ns apart. The TLV3201-Q1 has a propagation delay of up to 50 ns.

    The TLV3201-Q1 does not run at 1.8 V, but no fast comparator does. You need a separate buffer to shift the comparator's output down to 1.8 V, e.g., SN74AUP1T34-Q1.
  • 0 in reply to Shinji Tsuji
    TI__Expert 4555 points
    Shinji,

    As Clemens stated, the TLV3201 has a max propagation delay of 50ns, which is too large for a 20MHz signal.

    I would recommend the TLV3501 which has a typical propagation delay of 4.5ns, and is also available in a Q-grade version.

    Unfortunately, you are going to have alot of trouble finding a high speed comparator that can operate down to 1.8V. The best solution without affecting the timing of the signal would be using a high speed logic buffer.
  • 0 in reply to Jonathan Nguyen
    TI__Genius 13118 points

    Thank you for the reply.

    Initially I consider a logic buffer, but it turned out that the input threshold is too wide for this 0.8V clipped sine wave and Emrys suggested me to look for comparator product in the top of this thread :)

    If I have 2.5V or 3.3V rail in the board and could supply TLV3501-q1, is there any problem?

    Is there any concern receiving 20MHz clipped sine clock at 0.8Vpp by TLV3501 and then level shift by a logic buffer?

    By the way since the signal is clock, if absolute delay is fixed, I don’t care so much about the propagation delay. Is my understanding correct?

    Regards,

  • 0 in reply to Shinji Tsuji
    Guru 277220 points
    The TLV3201-Q1's propagation delay can be as long as the high/low period of your clock signal. So it might technically work, but if the low-to-high and high-to-low propagation delays are not identical, you might get quite a large pulse width distortion.

    The TLV3501A-Q1 will work fine, if you shift its output signal down to 1.8 V with a buffer like the SN74AUP1T34-Q1.
  • 0 in reply to Clemens Ladisch
    TI__Genius 13118 points

    Hi,

    Does SN74LVC1G04QDBVRQ1 also work for the voltage translation purpose?

    Since 3.3V to 1.8V translation, I think this could work.

    regards,

  • 0 in reply to Shinji Tsuji
    Guru 277220 points
    Yes; the SN74LVC1G04-Q1's input is overvoltage tolerant, and it supports 80 MHz at 1.8 V.
  • 0 in reply to Shinji Tsuji
    TI__Expert 4555 points

    Shinji,

    The minimum operating voltage of the TLV3501-Q1 is 2.7V, so you will need to power it off of a 3.3V rail.

    To have the delay be absolutely fixed, (Low to High/High to Low and rise/fall times are symmetrical) you need to ensure that the input signal crossing the threshold crosses at the 50% level of your input signal.

    For example if your switching threshold was 1.5V, and you have a 500mVpp signal you are monitoring, you would want to ensure that your input signal goes 250mV above the threshold (overdrive) and 250mV below the threshold (underdrive).

    If your overdrive and underdrive are not equal, then your switching characteristics will be asymmetrical from low-high/high-low transitions which will cause frequency inaccuracy from monitoring your 20MHz clock. 

    Regards,

    Jonny