Other Parts Discussed in Thread: TXS0104E, TXB0104
My Dear customer would like to use the TXB0304, and play as a level shifter at Intel Gemini Lake with LPC ( Low Pin Count ) Interface.
Two questions here that need your quick to reply.
Q1. Can TXB0304 device be operated as Open Drain at 25Mhz output at Intel's LPC during below TAR phase??
- 1. LPC TAR phase requirement:
This field is two clocks wide, and is driven by the host when it is turning control over to the
peripheral, (for example, to read data), and is driven by the peripheral when it is turning control
back over to the host.
On the first clock of this two clock wide field, the host or peripheral drives the LAD[3:0] lines to
‘1111b’. On the second clock of this field, the host or peripheral tri-states the LAD[3:0] lines.
Since these lines have weak pull-ups on them, they will remain at a logical high state.
Q2: Do we need to use pull up resistor at output side for LPC? IF yes, may I know its value.