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Original question:

SN74AXC8T245: What is guaranteed output skew?

SN74AXC8T245: part to part skew for large bus data rate

William Gavert
Prodigy 20 points
Part Number: SN74AXC8T245

I have a data bus that is 64bits with an output clock at rate of 125MHz. The VA side is 3.3V the VB side is 1.8V into an FPGA.

Most of the applications such as RGMII  share the clock with the data on the same part.

For a single part this is fine since the internal skew is around 104ps. 

I need to have four parts for data and one for the clock. Is the a part to part skew low enough to do this?

Thank you,

Bill

  • 0
    TI__Mastermind 45725 points

    Hi William,

    Worst case part to part skew will be determined by the difference between the max and min propagation spec.

  • 0 in reply to Dylan Hubbard
    Prodigy 20 points

    Dylan,

    Thank you for the quick response. I just need some clarification.

    How much of the min and max propagation delay times are due to temperature versus component to component differences.

    When I read the min and max I could assume that at one temperature I may have a worst case min propagation time and at some other  temperature it is a worst case max. 

    if this has a strong temperature relationship, then the propagation delay would be similar between parts at the similar temperatures. I would not have one part at -40 and another at 125C they may only be within 5 degrees of each other.

    Thank you,

    Bill

  • 0 in reply to William Gavert
    TI__Mastermind 45725 points

    Hey Bill,

    I won't be able to provide you with how much temp impacts the value versus process skew, but I can say that we've seen  2 of these devices used for RGMII by other customers without facing any issues.