Hi,
in the datasheet we have shift register and storage register
Do I understand it correctly below?
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Hi,
in the datasheet we have shift register and storage register
Do I understand it correctly below?
Clemens,
thanks.
I wonder why the output state of QA to QH are all determined after only one clock cycle as shown below:
In my mind, QA will be determined after the first clock, QB won't be determined until the second clock, and so on.
After the first clock, the first shift register will be the same as SER, and the second shift register will be the same as the first one(which is undetermined when powered up I think).
Pulling SRCLR low forces all eight bits of the shift register to zero. The RCLK pulse then copies these eight bits to the storage registers.