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SN74LV4046A: PLL Resistor and Capacitor Values

Thomas Jacobson
Intellectual 310 points
Part Number: SN74LV4046A
Other Parts Discussed in Thread: CD74HC4046A

Hello everyone,

We are working with the PLL to boost a 60 Hz signal up to a signal that oscillates 2^18 times faster, roughly 15.728 MHz. The input signal can vary from about 40 Hz to 70 Hz, so the output from the PLL needs to have a range of about 10 MHz to 20 MHz.

We've had trouble getting the output signal to the right frequency. Currently it's at 400 kHz, which appears to be the minimum offset frequency. The person who designed our PLL is looking into the correct resistor and capacitor values for R1, R2, C1, R3, and C2. But I've also been doing some research since we can't really move forward until this is resolved. We've tried a couple different combinations, but nothing has gotten us into the MHz range.

I've looked a lot at the App Note for an older generation of the PLL (http://www.ti.com/lit/an/scha003b/scha003b.pdf). However, I've haven't worked with a PLL before, so I'm struggling to grasp what size resistors and capacitors we need. Also, since this older PLL seems to rely on higher voltages, I'm concerned that some of the documentation doesn't really translate to the newer part.

Does anyone have any insights into what values I should use for the resistors and capacitors? Or is there another reference I could use that might help?

Thanks,

- Tom

  • 0
    TI__Guru* 97046 points

    Hi Tom,

    This device was designed to be a drop-in replacement for the previous generation of devices, so you will find that all of the design techniques used for the older parts will work for this one as well.

    With such a slow input signal, it will probably be very difficult to maintain precise phase alignment between the input signal and the final waveform. Can you share why you chose this solution as opposed to generating a clock separately, for example using an MCU + crystal, then using that to monitor/generate the clock output? I can't imagine the phase alignment between a 40 Hz signal and a 10 MHz signal would need to be very precise (even 180 degrees out of phase for the 10 MHz signal results in only 50ns of error, or 0.0002% phase error at 40 Hz)

    If you'd like to use your current circuit to figure out what's going on (which I what I would do), the first step for troubleshooting I would recommend is to disconnect the signal input to VCO_IN and replace it with a DC voltage source. You can vary that from 0V to Vcc (3.3V?) to directly measure the VCO output frequency range with your current choice of resistors/capacitors.

    I would also recommend looking at the input signal waveform at SIG_IN and ensure that it has fast/clean edges (preferably under 10ns/V transition times). Slow edges at the input can result in false triggers and internal oscillations that can cause unexpected operation. 

    My starting point for the passive components would be:

    R1 = R2 ~= 15 kohm

    C1 ~= 18 pF

    Assuming you are operating at ~3V

    R2 & C1 are determined by desired offset, using figure 28 in the CD74HC4046A datasheet

    R1 = R2 because the desired frequency range is 20 MHz to 10 MHz (fmax / fmin = 2). From the CD74HC4046A datasheet, figure 31 indicates that the ratio of R2/R1 = 1 for fmax/min = 2

    I would then prototype the design and adjust values until I had the right range for desired operation.

  • 0 in reply to Emrys Maier
    Intellectual 310 points

    Hi Emrys,

    Thanks for your response. I'll connect a DC source to see what the VCO_OUT looks like. And I'll try your starting values for R1, R2, and C1 as well.

    I'm not sure why a PLL was picked initially. I mostly work on the firmware rather than the hardware design. I do know that the frequency can vary, so however we multiply the frequency, it needs to be able to update on-the-fly.

    Is it safe to ignore the SN74LV4046's datasheet when it claims that C1 must be greater than 40 pF? If this is supposed to be a drop-in replacement, and the older part could go below that capacitance, then I'd assume the newer part could as well.

    - Tom

  • 0 in reply to Thomas Jacobson
    TI__Guru* 97046 points

    Hey Tom,

    You're right - I shouldn't have gone below the datasheet minimum. I thought of that while I was writing my response, but got distracted and forgot. Sorry about that.  The device is tested with C1 = open, so I don't see a problem with running it below 40pF, but being outside datasheet spec means TI can't guarantee operation. ie it will probably work, but we can't be certain of stability.

    I think you're going to be operating very near the limits of the device, so you may have to start with the datasheet minimum values of R1 = R2 = 5.4 kohm and C1 = 40pF, then adjust to try to meet the requirement.

  • 0 in reply to Emrys Maier
    Intellectual 310 points

    Good morning Emrys,

    Your suggestions got us on the right path. We were able to toggle the VCO_IN line with a DC power supply, and saw the frequency range. We are going with a 39 pF capacitor and two 7.5 kohm resistors for R1 and R2. We may need to make more changes, but we have the PLL working now. Thank you for your help.

    - Tom

  • 0 in reply to Thomas Jacobson
    TI__Guru* 97046 points

    Hey Tom,
    I'm glad I could be of help.  Please come back any time!