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SN74LVC1G74: SN74LVC1G74

Anuraj nk
Intellectual 330 points
Part Number: SN74LVC1G74
Other Parts Discussed in Thread: SN74HCS74

Hi,

 I am using the part "SN74LVC1G74" in my design.  The block diagram is as mentioned below.

CLR#, PRE# and Q is connected to Processor. Q# is not connected. CLK is connected to timer circuit and Q should go high only if any Rising Edge is found on the Timer output. Data pin is connected to VCC always.

 

I am doing DO-160 power interrupt test on the system level and have below observation.

‘Q’ output is going high when I do D0160 power interrupt test on system level.

I have 50ms hold up time in system level. When I do the power interrupt test for 20ms, my system should not restart and it continue working as earlier.

When I do the power interrupt for 20ms, Q is going to High, which is not supposed to. I have probed all the signal during this test and no trigger is observed on any of the signals.

Please guide me to understand the reason for this. Let me know if any additional information is required.

Probing Points are mentioned below.

 

Waveform 1 :
CH1 : CLK 
CH2: Q
CH3 : CLR#
CH4 : PRE#
  

Waveform 2 :
CH1 : Data

CH2 : Q

 I am using the part "SN74LVC1G74" in my design.  The block diagram is as mentioned below.

CLR#, PRE# and Q is connected to Processor. Q# is not connected. CLK is connected to timer circuit and Q should go high only if any Rising Edge is found on the Timer output. Data pin is connected to VCC always.

 

I am doing DO160 power interrupt Test on the system level and have below observation.

‘Q’ output is going high when I do D0160 power interrupt test on system level.

I have 50ms hold up time in system level. When I do the power interrupt test for 20ms, my system should not restart and it work as how it was working before 20ms.

When I do the power interrupt for 20ms, Q is going to High, which is not supposed to. I have probed all the signal during this test and no trigger is observed on any of the signals.

Please guide me to understand the reason for this. Let me know if any additional information is required.

  • 0
    Guru 316780 points

    The Recommended Operating Conditions table shows that the output value might change when the power supply goes below 1.5 V.

    To ensure a known output state after power was interrupted, the processor must pull CLR low in that situation. (If the processor outputs go high impedance, you could add a pull-down resistor.)

  • 0 in reply to Clemens Ladisch
    Intellectual 330 points

    Power interupt for 20ms wont make to Latch supply goes off. We have 50ms holdup from power supply card.

  • 0 in reply to Anuraj nk
    Guru 316780 points

    If the power supply does not sag, then there must be something else that affects the flip-flop state. Please zoom in on the PRE/CLK signals, into the nanosecond range.

  • 0 in reply to Clemens Ladisch
    TI__Genius 16735 points

    Hi Anuraj,

    I will also recommend your provide me with the same as clemens has mentioned:

    Please zoom in on the PRE/CLK signals, into the nanosecond range. There may a small noisy edge that could cause the false trigger to happen.

    Thanks!

    -Karan

  • 0 in reply to Karan Kotadia
    Intellectual 330 points

    I probed the PRE /CLK signals in nano second range and not seen any edge in the signal. CLK stays in low and PRE to high state.

  • 0 in reply to Anuraj nk
    TI__Genius 16735 points

    Hi,

    So there is no noise on your CLK, PRE or CLR pins correct?

    Can you explain to me what happens a power interrupt test is done? If all the input signals were holding their state then there can be no changes in the output.

    Thanks!

    -Karan

  • 0 in reply to Karan Kotadia
    Intellectual 330 points

    Today i probed with high resolution scope and i got some glitches in the signals. Please find the attached waveform.

    Is this glitch enough to latch the output (Q) high ?? Glitch in which pin is causing the issue?

  • 0 in reply to Anuraj nk
    TI__Genius 16735 points

    Hi,

    The threshold at which a change in input will cause a change in output is around half Vcc. All 3 of your signals could be reaching that state, hence the large number of oscillations on your output.

    Have PRE go low, will cause Q to go to a High, is Clear able to stay high during this?

    Having data oscillate while clock is oscillating will also explain the oscillations on the output.

    The quickest solution might be to switch the part to the SN74HCS74 which has schmitt trigger inputs to provide immunity to slow and noisy input signals.

    Another solution, since you don't need a high frequency signal will be to add a RC to your inputs to damp the input oscillations. Be careful with this as your input signal edges should not become so slow as to violate the minimum input edge rate requirements in the datasheet.

    Thanks!

    -Karan

  • 0 in reply to Karan Kotadia
    Intellectual 330 points

    Thanks Karan. I am planning to switch to new part  with schmitt trigger inputs. Can you suggest  a part which is drop and replacement for the existing part (SNLVC1G74). The boards is already assembled and at this stage it is difficult to go for a re spin.

  • 0 in reply to Anuraj nk
    TI__Genius 16735 points

    Hi Anuraj,

    Unfortunately the only flip flop with all schmitt-trigger inputs is the, SN74HCS74. There is no p2p drop in replacement, you will have to modify the board to be able to fix this.

    Thanks!

    -Karan