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LSF0101: Spice Modeling

Part Number: LSF0101

Is there a Spice model available for these parts? 

If not, then is there a parameter set for the internal MOSFET so I could kludge my own?  

My design has VREF_B at 3.3V.    The other side will be varied by the application per the customer's spec.   The range of the "A" side is 1.8V to 3.3V.     At the 3.3V level on "A", there is not enough difference between "B" and "A".     Using the app note,  I formed VREF_A from a resistor voltage divider derived from 3.3V.     I set the VREF_A voltage at 1.5V .    Seems like it will work, but  I would like to have simulation examples to prove to the rest of team that the solution is viable.

Thanks.

 

  • Hi Steve,

    Welcome to e2e. You could use a generic NFET model on Pspice / LTspice to simulate the behaviour of the LSF.

    For more information on single supply level translation refer to the LSF video tutorials here below:

    LSF0101.TSC

    Here is the TINA spice model which I use.

    Let me know if this works for you.

    Also, you could consider using our DIR controlled level translation which doesnt have the supply rails restriction on them. This allows to operate across the whole 1.8 <> 3.3V for both the Vcca / Vccb.

  • In fact, there is a SPICE model in the product folder of the LSF0101. Please let me know how it works out.

  • Thank you.  I was able to get your example circuit to work in TINA.    Because of the COVID-19  virus lockdown,  I do not have lab access to experimentally verify it.   I tried with the SPICE model to also simulate in LT Spice as another verification.  However, unfortunately the Spice model is encrypted, so LT Spice cannot use it.   So, I guess I have to just go with the TINA.    To anyone else wanting to simulate this part,  I would suggest using TINA. 

  • Thank you for the suggestion.

    Stay home and stay safe !