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Dear Team,
I learn from another E2E question that there is a DC offset when logic low. And we can increase pullup resistor value to improve this offset.
https://e2e.ti.com/support/logic/f/151/t/889635?tisearch=e2e-sitesearch&keymatch=LSF0102
But my customer would like to know if TI has another level-shift solution that has no offset when logic low.
Do you have any suggestion?
Thank you.
Regards,
Jim
Hi Jim,
Here is a list of translators that should be better for this: http://www.ti.com/logic-circuit/voltage-level-translation/direction-controlled-voltage-translation/products.html.
Hi Dylan,
From your list, I would like to propose SN74AXC2T45 and SN74AXCH2T45 to my customer.
Could you help to confirm these two solution has no offset when logic level low?
Thank you.
Regards,
Jim
Hi Jim,
The SN74AXC2T45 is a good selection. Low level offset is indicated in the data sheet with Vol. If you are just driving another high impedance digital input, then the low level voltage will be GND.