Other Parts Discussed in Thread: SN74AXCH2T45, SN74AXC2T45
Dear Team,
I learn from another E2E question that there is a DC offset when logic low. And we can increase pullup resistor value to improve this offset.
https://e2e.ti.com/support/logic/f/151/t/889635?tisearch=e2e-sitesearch&keymatch=LSF0102
But my customer would like to know if TI has another level-shift solution that has no offset when logic low.
Do you have any suggestion?
Thank you.
Regards,
Jim