Dear Support;
This is the first time I am using this family of passive level translators. I have two applications and need help with the first and verification of the second. Thank you in advance for your support!
Application A
In my first application shown below, I need to provide a logical pull-down function of the 1.8V FPGA I/O signals connected to the A port. I want to guarantee that the up translated outputs are low during FPGA configuration while the FPGA pins are tri-stated. I do not believe the circuit shown below can work since the relatively weak 2.2k pull-downs will cause the FETs to turn ON (source below 1.8V bias level internally) and the FET will conduct connecting the pulled down node on the A port to B port the 330 ohm pull-up to 3.3V. This I believe leads a 330/2.2K voltage divider and will NOT provide a low state voltage at port B. Is my understanding correct? If so, is there a way to provide the translation and an active low power up state? I am trying to avoid adding an additional driver just to handle the power-up case while the FPGA gets configured.
In my second application, I am using a single chip to provide multi-voltage translation. One case is uni-directional up translation from 1.8V to 3.3V. In this case, the A side is operated at the lowest interface voltage of 1.8V and the 3.3V pull-ups are optional based upon leakage in the 3.3V receiver and I have chosen to include.
The second translation if for a bi-directional I2C bus with up translation from 3.3V to 5V and down translation from 5V to 3.3V. I believe that as long as the A port is operated t the lowest interface voltage of 1.8V, then the pull-ups to 3.3V and 5V allow for the correct bi-directional translation between 3.3V and 5V. Is this design correct
