SN74LVC244A-Q1: Slew Limitation on Enable pin

Jared Becker

Part Number: SN74LVC244A-Q1

Hi Team,

Is there an slew rate limitation for the enable pin of the SN74LVC244A-Q1? I want to verify that if a fast signal is switching the enable pin that an ESD cell does not become activated or anything like that.

Thank you!

Jared

over 5 years ago

0 Clemens Ladisch over 5 years ago

Guru 316880 points

This is not a characteristic of this device, or of any other CMOS input.

A fast slew rate can indeed cause ringing, but whether this happens depends on the trace length, the presence of parasitic capacitances and inductances, and how the trace is terminated. If the trace is longer than four inches, you might need to simulate or measure the board. (For how to terminate long traces, see page 1-27 of the LVC Designer's Guide.)

0 Jared Becker over 5 years ago in reply to Clemens Ladisch

TI__Genius 11845 points

Hello Clemens,

Thank you for the response! May I also ask if there are any slew rate limitations for the VCC pin?

Thank you,

Jared

0 Clemens Ladisch over 5 years ago in reply to Jared Becker

Guru 316880 points

Are you asking for a minimum or a maximum limit? The decoupling capacitor will prevent you from exceeding any reasonable upper limit, and there is no lower limit (although the device is not guaranteed to work correctly while V_CC is above 0 V and below 1.5 V).

0 Jared Becker over 5 years ago in reply to Clemens Ladisch

TI__Genius 11845 points

I am asking for a maximum limit. The voltage at the VCC pin is from 0V to 3.3V in <1ms. Will that be acceptable?

Thanks!

Jared

0 Clemens Ladisch over 5 years ago in reply to Jared Becker

Guru 316880 points

As I said, there is no minimum limit on the slew rate.

Logic

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SN74LVC244A-Q1: Slew Limitation on Enable pin