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SN74LV1T04: Was the waveform in datasheet of SN74LV1T04 taken with other device?

Part Number: SN74LV1T04

 Hello guys,

 One of my customers is considering using SN74LV1T04 for their new products.

 They have a few questions about the datasheet as the follows.

 Could you please give me your comments or reply?

 Q1. On page 3 of the datasheet, "Figure 1. Logic Diagram (NAND Gate)" is described. What is the mean of "NAND gate"? Is this a typo? Correctly is it "INVERTER gate?

 Q2. On page 3, Figure 2 waveform seems taken with buffer logic. Is it correct? Also is the waveform just typical data of this logic series as a exsample?

 Your reply would be much appreciated.

 Best regards,


  • The datasheets of all devices listed in section 5.1 were created at the same time, so I guess a lot of copy+paste was involved.

    The waveform is indeed typical, and applies to all devices in the family. For the inverter (or the NAND gate), the polarity would of course be inverted.

    (What is the customer's application? While LV1T is very flexible regarding voltages, downconverting with AHC1G devices or upconverting from 3.3 V to 5 V with AHCT1G devices might be cheaper.)