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Original question:

SN74LVC1G58: VT+ threshold range on 5V vcc

SN74LVC1G58: input inpededance in unpowered condition

Guenter Goldbach
Prodigy 70 points
Part Number: SN74LVC1G58

Hi,

according to the datasheet the absolut max input voltage VI is -0.1 to 6.5V and VO even in unpowered state is allowed in teh same range.

Does this mean that any logic level below 6.5V would not damage the device even if power is not available? Or in other words, the ESD clamps and substrate diodes do not cause low impednace in unpowered condition?

Is there any specification or a rough estimation for the imput impedenace in unpowered state?

I assume that the SPICE model is only valid in powered state, correct?

Günter

  • 0
    TI__Expert 6680 points

    Hi Günter,

    While it might say that 6.5V is the maximum input voltage, we recommend following the maximum in the "recommended operating conditions" as stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These absolute maximum ratings are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may also affect device reliability.

    That being said, yes, this device should be able to handle an input voltage up to 5.5V even when VCC is 0V.

    Thanks!

    Chad Crosby