SN74LVCH8T245: Delay time calculation

Muthu A

Part Number: SN74LVCH8T245
Other Parts Discussed in Thread: SN74LVCH16T245

Hi,

I have a doubt in estimating the maximum propagation delay for SN74LVCH8T245 when changing the DIR signal. For ex: My Vcca=5V & Vccb=3.3V. Initial data flow direction is from A to B (DIR=HIGH). If I change the DIR to LOW, how much time it would take to reflect the B side signals at A side?

Datasheet specifies,

I have two questions here.

1) I'm not sure which equation should I consider? Is it 1 or 2 or both.

2) We see a time delay to disable B port (tpLz/tpHz) & normal signal propagation delay (tpLH/tpHL). Should there be a time delay to enable the A port or is it already enabled?

Also datasheet spec says,

3) If tpzH (or) tpzL is the total delay from the moment we change the DIR signal & to get output signal at desired side (as per first screenshot), why tphZ/tpLz (~8ns) is specified more than tpzH /tpzL (~6ns). Please help me to have a correct understanding.

Thanks & Regards

Muthu A

over 5 years ago

0 Muthu A over 5 years ago

Intellectual 330 points

attaching the screenshots and respective datasheet section number again as they are not getting displayed.

First screenshot: equations from section 9.2.2.1

second screenshot: switching characteristics from 3.9

0 Clemens Ladisch over 5 years ago

Guru 318700 points

As shown in the logic diagram, the input buffers on both sides are always active. So changing the DIR input only disables and enables the output buffers. Therefore, the time from changing DIR to low until the A pin outputs a signal is t_PZx.

However, the value at the B input was determined by the active B output. If the new value imposed by the external device is different from the old value, then the total time is t_PxZ plus the propagation delay (t_PLH or t_PHL).

0 Muthu A over 5 years ago in reply to Clemens Ladisch

Intellectual 330 points

Thank you Clemens.

In case of SN74LVCH16T245, to get worst case tpzx, should I add tpxz & tpLH/tpHL (or) I can directly take it from the datasheet's "switching characteristics". Because the summation and the value given as a total tpZX given in datasheet are different.

Thanks & Regards

Muthu A

0 Clemens Ladisch over 5 years ago in reply to Muthu A

Guru 318700 points

These are two different cases. So for the worst case, take the larger one.

0 Muthu A over 5 years ago in reply to Clemens Ladisch

Intellectual 330 points

could you please suggest if there are any other bi-directional buffers which could give lower propagation delay than this.

Thanks & Regards

Muthu A

0 Clemens Ladisch over 5 years ago in reply to Muthu A

Guru 318700 points

At 5 V, LVC is the fastest logic family. If you had at most 3.3 V, AXC translators would be faster.

0 Muthu A over 5 years ago in reply to Clemens Ladisch

Intellectual 330 points

Thank you Clemens.

One final question. What is the time delay for enabling and disabling the level-shifter with OE line. Is it tpZx & tpXz respectively?

Thanks & Regards

Muthu A

0 Clemens Ladisch over 5 years ago in reply to Muthu A

Guru 318700 points

As far as the specifications are concerned, there is no difference between DIR and OE.

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SN74LVCH8T245: Delay time calculation