Part Number: LSF0108
Hi Tean,
My customer has the following questions and they requests the answers.
Would you please check them from you?
Customer is considering the signal interface between 3.3V CPU and 1.8V communication device and checking Figure-6 on datasheet.
SDIO interface/ 25MHz CLK
Q1: On the Figure-6 on datasheet, Rpu(pullup resisters) has illustrated on both 3.3V and 1.8V sides. Are the pull-up resisters needed on both sides?
Q2: There is the description that the pull-up resisters must limit the current flowing through PASS-SW to <15mA. But according to Table-5, the pull-up resister for three current values(15m, 5m and 3m) is been showing.
-a): To keep pass current <15mA is only limitation. Is this understanding correct?
-b): Is there any limitation about minimum current flowing through PASS-SW? If so, How much current is it?
-c): If the pull up resisters on both 3.3V and 1.8V sides are needed, is it OK to use 10k for all pulup resisters on both sides?
Q3: Is it OK to connect the 200k resister on VREF_B pin directly to Vpu(3.3v)?
Q4: How is the I/O pins(Ax & Bx) of unused channels handled?
Q5: How is the bidirectional signal operation achieved on this Figure-6 configuration?
Q6: Is there any concern when used at 25MHz signal speed?
Regards,
H.Someno