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Hi, TI expert.
In order to prevent the pulse gate signal from appearing high at the same time in the customer, we want to configure the logic as follows.
I have a GATE device inquiry regarding that.
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- NAND GATE (2CH) : ?
- AND GATE (4CH) : ?
- Vcc: 3.3~5V
- Propagation Delay: 10ns or less
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Please recommend suitable NAND Gate and AND Gate.
Thank you.
NAND: SN74LVC2G00
AND: SN74AHC08 (The AHC propagation delay at 3.3 V is marginal. If this is important, use 2× SN74LVC2G08.)
This logic function (AND with one inverted input) could be implemented with just the SN74LVC1G97, but would require four single-gate chips.