SN74LVC1G123: About Output Pulse Duration vs External Timing Capacitance curve

Hey Yusuke,

Yes R_L in those figures will be the resistor that goes into the Rext. The resistor itself should be labeled as R_T, so this was mislabeled in the datasheet, so we'll need to go back and update it. 

As for selecting the correct C_T and R_T values, the Cext and Rext as you're calling them, you'll want to first pick the desired pulse width, then you'll want to pick a combination of the K factor from figure 6, C_T and R_T that will give you is according to the equation here:

 
Thanks,
Rami

Hey Yusuke,

Theoretically there isn't an upper limit. The minimum values are set such that the current draw won't damage the chip, so the upper limit isn't really a concern. Of course you'll have to take in account the trade-offs with size, price and tolerance of the passives. The higher the value, the more variance the tolerance will allow so you'll lose some precision in your timing. That is to say, 1% tolerance for a 5k won't have the same effects as 1% for a 50k. Larger resisters values are typically also physically larger as well. You'll need to take those things into account when selecting the values that best fit your application. 

Thanks,
Rami