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From TI reference design schematic, the CLK_INH pin connect to GND directly.
Does that CLK_INH always LOW be fine?
What happen if the SH/LD is "LOW"? Does IC will ignore the CLK and stop output serial data?
Connecting CLK_INH to GND is fine.
The datasheet says:
The parallel inputs to the register are enabled while SH/LD is held low, independently of the levels of CLK, CLK INH, or SER.
So in this state, the QH output always outputs the current value of the H input.