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SN74LVC2G08-Q1: SN74LVC2G08-Q1 - High and low level input thresholds

Part Number: SN74LVC2G08-Q1

Hi ,

I am using SN74LVC2G08-Q1 in my project application and I while validation I find some discrepancy in the output waveform. I have provided IN1 = 3.3V and have provided a triangular waveform with 10kHz at IN2. We can find from the waveform that high level input voltage is 1.774V and low level input voltage is 1.673V .I find these values different from those provided in the datasheet for VCC= 3.3V.Please explain the deviation.

  • TI guarantees that any voltage above VIH (2 V) is read as high, and that any voltage below VIL (0.8 V) is read as low. There is no guarantee for any voltage between those thresholds. This behaviour conforms to the specification.

    And that triangular waveform violates the Δt/Δv limit. See [FAQ] How does a slow or floating input affect a CMOS device?

    And you have to ensure that the inputs of the other AND gate have valid logic levels.

  • Hi Clemens, 

    Thanks for your reply.

    Can you please let me know at what frequency the input can be operated. I see that the transition rate for the input as mentioned in the datasheet is 10ns/V.

    I am providing Vcc= 3.3V. As I understand it the minimum input frequency is 1/30nS = 33.3 MHz

    Am I correct?

  • For digital signals, the Δt/Δv limit has nothing to do with frequency; it describes how fast edges must be. There is no minimum input frequency. The maximum is limited by the outputs, and is 87.5 MHz (175 Mbps) with CL = 50 pF.

    For such an analog signal that never stays at VCC or GND, you indeed have to make the frequency high enough that the slope is steep enough. There are two edges in one cycle, so the minimum frequency for a triangle wave would be 15.15 MHz.

    Slow edges are forbidden because they will cause greatly increased power consumption und possibly oscillations, but you will still be able to measure the switching thresholds.