This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

AM2434: GPIO Interrupt

Part Number: AM2434
Other Parts Discussed in Thread: SYSCONFIG

Customer currently have an issue with GPIO interrupt. They need 2 or more interrupts must be supported. They want to use gpio router8 and route9 same time. but, only router9 is working.  

it seems that they can use some interrupt routers on TI SDK 08.06.00.43, but they are blocked as they are using  08_05_00_24 that has some limitation on this?  Can they use only one interrupt router at same time on SDK 08_05_00_24? Is there a way around this?  

 

They are using TI SDK 8.5 now, but we can’t change TI SDK version because the bootloader they are using based on SDK 8.5 and they cannot field upgrade units to a newer SDK version.

  • Hello Lawrence,

    Thanks for reaching out to Texas Instruments E2E support forum.

    I have taken your inputs and working on it. Please allow some time to revert back.

    Regards,

    Tushar

  • Hello Lawrence,

    Can you please tell us more about the usecase?

    Which GPIO pins are you using? And what are destination cores on which you want to route the interrupt?

    Thanks & Regards,

    Tushar

  • Hi Tushar,

    Information from customer:

    They modified k3BoardConfig.json with reference to TI SDK 08.06.00.45.

    ROUTER 0 to 7 are defined in r5fss0-0 settings of TI SDK 08.06.00.45, so they added ROUTER 0 to 7 and changed the sysconfig, but an assert error occurred when bring up MCU.

     

    ASSERT: 1.312833s: generated/pinfire-mcu-sm-app/ti_drivers_config.c:Sciclient_gpioIrqSet:104: FALSE failed !!!

     

    sysconfig

    ---------------------------------------------------------

    gpio18.$name                = "USB_PD_IRQ";

    gpio18.trigType             = "FALL_EDGE";

    gpio18.advanced             = true;

    gpio18.intrOut              = "0";

    gpio18.GPIO.gpioPin.$assign = "ball.M2";

     

     

    gpio30.$name                = "CODEC_IRQ";

    gpio30.GPIO.gpioPin.$assign = "ball.AA4";

    gpio30.trigType             = "RISE_EDGE";

    gpio30.advanced             = true;

    gpio30.intrOut              = "1";

    ---------------------------------------------------------

    Is that enough information to investigate?

    Regards,

    Lawrence

  • Customer currently have an issue with GPIO interrupt. They need 2 or more interrupts must be supported. They want to use gpio router8 and route9 same time. but, only router9 is working.  

    it seems that they can use some interrupt routers on TI SDK 08.06.00.43, but they are blocked as they are using  08_05_00_24 that has some limitation on this?  Can they use only one interrupt router at same time on SDK 08_05_00_24? Is there a way around this?  

    Hello Lawrence,

     Customers no need to go to the newer version for just updating board cfg file .

    We can update the board cfg file as per the customer requirements.

    I have looked at the below. The information related to GPIO. One is M2 and another one is AA4. So, based on the datasheet the I came to know M2 pin the belongs to DDR_M1, which can't be controlled by the user. I assume that these pin details might be wrong.

    Actually, we are expecting like there are GPIO0 , GPIO1 and  MCU_GPIO pins are avaialble on AM243X.

    I assume that GPIO_0 port pins they wanted to route to the M4F core ?

    If you share details like GPIO_0_13 and GPIO_0_14 pins need to Route M4F then it  is really helpful.

    Regards,

    S.Anil.

  • Hi Swargam,

    Just to clarify customer is using the ALX package not the ALV package so that could be part of the disconnect in the information above.  Let me clarify with customer.

    Regards,

    Lawrence

  • Hi Swargam,

    Update from customer:

    ==========

    We were able to use both gpio router 8 and router 9.

    The cause was that the value returned by Board_getGpioButtonIntrNum() was always the same.

    We solved it by 8 and 9 fixed values.

     

    /* This is based on DMSC board config and core */

    #define BOARD_BUTTON_GPIO_INTR_NUM     (CSLR_R5FSS0_CORE0_INTR_MAIN_GPIOMUX_INTROUTER0_OUTP_`config.intrOut`)

     

     

    We have one more question. we cannot set the same gpio router for multiple GPIO pins as below.

     

    In our understanding that the same GPIO router number can be set for if same GPIO domain, and multiple GPIO interrupts can be identified by mask in the interrupt handler.

    Is this understanding correct?

    Could you please provide an example using multiple GPIO interrupts?

     

    gpio18.$name                = "XXX";

    gpio18.advanced             = true;

    gpio18.GPIO.gpioPin.$assign = "ball.V13";

    gpio18.trigType             = "RISE_EDGE";

    gpio18.intrOut              = "9";

     gpio30.$name                = "YYY";gpio30.advanced             = true;gpio30.GPIO.gpioPin.$assign = "ball.Y13";gpio30.trigType             = "RISE_EDGE";gpio30.intrOut              = "9"; 

    error: YYY (/drivers/gpio/gpio) intrOut: Same Interrupt Router lines cannot be selected

    =======

    Regards,

    Lawrence

  • Hello Lawrence,

    As per the SOC, it can support both Bank interrupts and Pin interrupts.

    Pin interrupt : 

    You will get an interruption for a single pin. 

    Bank Interrupt : 

    You will get an interruption for 16 pins. 

    In the interrupt routine, you have to check for the interrupt cause of which Pin.

    In our understanding that the same GPIO router number can be set for if same GPIO domain, and multiple GPIO interrupts can be identified by mask in the interrupt handler.

    Is this understanding correct?

    Could you please provide an example using multiple GPIO interrupts?

    Case 1 : You want to route GPIO0_0 and GPIO0_1 pin interrupts to R5F0_0

    As per TRM, a total of 16 GPIO interrupts are routed to all R5F cores . Please look at the image below.

    On the software side, you can look at the path below. Here, we allocate how many interrupts are routed to all R5F cres this can be configured based on customer requirements.

    Step1: Now, you can select the GPIO0_0 pin interrupt configuration in the system configuration like enable interrupt, pin trigger type and so on.

    Step2: For the next, you can select GPIO0_1 pin interrupt confirmation and there you won't enable an interrupt and just configure pin type as input and select trigger type.

    Why do you need to do step2 above is not the same as step1, Due to limitations of system config, but there is no limitation on SOC is routing same Bank pin interrupt to single router output .

    After doing 2 steps, enable interrupt and register an interrupt callback.

    In the interrupt routine, you need to check if an interrupt is triggered due to GPIO0_0 or GPIP0_1. Based on this you can process.

    I hope you cleared all your doubts. Please let me know if you still have questions .

    Regards,

    S. Anil.

  • Hi Swargam,

    Customer tried following the steps you showed and tested it, but it didn't work.

    Interrupt does not generate for TEST_PORT (AA5) which intrOut is not set.

    Attached files are customer test code for IRQ testing. (extracted only code related about IRQ) for your review

    https://e2e.ti.com/cfs-file/__key/communityserver-discussions-components-files/1042/0044.sample.syscfg

    0044.irq_sample.c

    Regards,

    Lawrence

  • Hello Lawrence ,

    Can you please confirm , Customer wants to enable an interrupt for GPIO0_30 and GPIO0_31 Pins ?

    Regards,

    S.Anil.

  • Hi Swargam,

    Thats correct they need more GPIO pins to be interrupt input. They are using the ALX package if that makes any difference.

    Regards,

    Lawrence

  • Hello Lawrence,

    I can provide code by today for your above requirement .

    Regards,

    S.Anil.

  • Hello Lawrence,

    The example below is created on AM64X and the same method is applicable on AM243 for all packages.

    I have created a total of 4 GPIO interrupts.

    1 GPIO pin will come under Bank 3 and Router 0 interrupt is Routed to the R5F core. 

    3 GPIO pins will come under Bank 2 and Router 1 interrupt is Routed to R5F core .

    So, if input pins come under the same bank, then we need one interrupt, which is enough to process all the same pin interrupts. So, for this reason, we have used one interrupt for the above 3 pins.

    If input pins comes under different banks then we must need to go with different router interrupts .

    Please go through the example and let me know if you still have questions.

    I hope this example clears customer queries.

    3286.gpio_input_interrupt_am64x-evm_r5fss0-0_nortos_ti-arm-clang.zip

    Regards,

    Anil.