RM48L952: Checking ESM flags when injecting memory errors

Hi,

I am testing some code that monitors the ESM flags in group 1-3. I am trying to inject faults and see that the corresponding ESM error is set.

First I implemented a test to inject error to the Lock-step compare, I did this simply by writing 0x9 to KEYR register. 
The ESM error bit 2 in Group 2 is set accordingly as expected, so the test seems fine.
 

Then I tried to implement error injection for RAM ECC. I did so by the following code:

#define TCRAM_SYN_2BIT_DATA_ECC ((uint64_t)0x0303030303030303U) /* this corrupts the ecc with 2 bit error */
#define TCRAM_RAMCTRL_ECCWREN ((tU32)(1u << 8u))

/* 16 byte alignment is required to ensure that the starting address is always an even bank */
#pragma DATA_ALIGN(g_sramEccTest_arr, 16);
volatile uint64_t g_sramEccTest_arr[2] = {0u};

static void injectErrorRAMECC(const tB evenBank)
{
    volatile uint64_t ramread = 0U;
    volatile uint64_t* eccX;
    uint8_t testIdx = evenBank ? 0u:1u;

    /* Update ECC */
    g_sramEccTest_arr[testIdx] = 0u;

    eccX = &g_sramEccTest_arr[testIdx];
    eccX = eccX + (0x00400000u/sizeof(uint64)); // ECC is stored with an offset of 0x400000

    /* Enable writes to ECC RAM */
    tcram1REG->RAMCTRL |= TCRAM_RAMCTRL_ECCWREN;
    tcram2REG->RAMCTRL |= TCRAM_RAMCTRL_ECCWREN;

    /* Disable RAM ECC */
    _coreDisableRamEcc_();

    /* Force a double bit error */
    *eccX ^= TCRAM_SYN_2BIT_DATA_ECC;

    /* Enable RAM ECC */
    _coreEnableRamEcc_();

    /* Disable writes to ECC RAM */
    tcram1REG->RAMCTRL &= ~TCRAM_RAMCTRL_ECCWREN;
    tcram2REG->RAMCTRL &= ~TCRAM_RAMCTRL_ECCWREN;

    /* Read the corrupted data to generate error */
    ramread = g_sramEccTest_arr[testIdx];
}

When line 38 (ramread = g_sramEccTest_arr[testIdx];) is executed above the MCU seems to reset directly, so I am not able to verify that corresponding bit in ESM register is set.
I think _dabort should be called and then it should continue execution from the next instruction, but seems like _dabort is not executed until after the reset.

Any idea what might be the problem?

Also I am wondering what is the difference between errors considered as RAM uncorrectable error and RAM ECC uncorrectable error? I didn't find any way to inject other error than RAM ECC error in the SafeTILib.

Best regards