TMS570LS3137: PBIST module register RINFOL and RINFOU cannot be changed

Hi Chuck,

After PBIST clock is enabled by writing 0x1 to PACT register, you can write value to RINFOL and RINFOU. I just tried, there is no problem.

What is the HCLK frequency in your setup? The ROM clock is HCLK/1, or /2, or /4 or /8. 

You can use the code generated by HALCOGen:

pbistRun()

Hi QJ,

That's weird! I've the same setup as your code except I write PACT=1 and yours PACT=3, and both RINFOx register are changed to 0xFFFFFFFF as soon as PACT is set to 1, and cannot be overwritten with code, and even not possible to change even with direct register write in the Debugger's PBIST registers window.

HCLK is 100 MHz and PBIST ROM clock is /(1+1) so 50 MHz.

Could it be locked by a bit or something? 

Hi QJ,

Yes thank you, the OVER bit is a write-enable gate for the RINFOx registers, I've missed this one but I think that the RM is not clear on it, now with it set to 0x1, I can write and initiate the testing now.

However, a subsequent issue unknown to me always lead me to the Prefetch_Handler(), as soon as the following is called and completedly executed to the last line of code, even though no error detected when checking the PBIST_FSRF0 bit.

I know that "Prefetch Abort Occurs when the CPU attempts to execute an instruction which has prefetched from an illegal address, ie. an address that the memory management subsystem has determined as inaccessible to the CPU in its current mode."

Do I have the right to do this self-tests with a Debugger?

With it hung within the Prefetch_Handler(), the target power is recycled so the same code is started without the Debugger, not working! "Connect to the running target" now finds it looping inside a non-specific FIQ handler.

Any clue?

Thanks.

void tagMcu::runMcuPbist()
{
    MSTGCR_bit.ROM_DIV = 1;     // VBUS=HCLK/2=50 MHz (90 MHz max)
    MSIENA = 0x00000001;        // enable PBIST controller (not yet self-test)
    MSTGCR_bit.MSTGENA = 0xA;   // enable PBIST self-test


    /*
    +--------------------------B-L-O-C-K---H-E-A-D-E-R------------------------+
    |                                                                         |
    | Ref.: TRM spnu499c 7.3.1 PBIST Sequence & 7.6 PBIST Example             |
    |                                                                         |
    | VBUS:HCLOK ratio is 1:2, hence PBIST will need to reset for 32 VBUS     |
    | cycles. Wait 32 VBUS cycles (or 64 CPU cycles): 0.64 us.                |
    |                                                                         |
    +-------------------------------------------------------------------------+
    */

    CLOCK.WaitUs(1);


    /*
    +--------------------------B-L-O-C-K---H-E-A-D-E-R------------------------+
    |                                                                         |
    |   Note: Launching self-tests for all single port RAM group.             |
    |                                                                         |
    +-------------------------------------------------------------------------+
    */

    PBIST_PACT  = 0x00000001;   // enable PBIST internal clock
    PBIST_OVER  = 0x00000001;   // update RAM info registers RINFOL and RINFOU
    PBIST_RINFOU= 0x00000000;   // device supports up to 28 ROM/RAM groups: upper register not needed
    PBIST_ROM   = 0x00000003;   // both algo and RAM info from ROM for application self-test

    PBIST_ALGO  = 0x00000008;   // select algorithm mask 0x8 (Single Port: MARCH13N_RED)
    PBIST_RINFOL= 0x08300020;   // select single port RAM group (ESRAM1,5,6,8)
    PBIST_OVER  = 0x00000000;   // RAM info registers RINFOL and RINFOU are used
    PBIST_DLR   = 0x00000014;   // config access and kick off the self-test

    // wait for the self-test to complete or first occurrence of test failed
    // if the while loop never ends, the watchdog will reset the MCU

    // ADI_SAFETYMCUSW_CHECK: <APPROVED> "Potentially infinite loop found
    // - Hardware status check for execution sequence"
    while (MSTCGSTAT_bit.MSTDONE != 1)
        continue;

    if (PBIST_FSRF0 == 0x01)    // detected error in port 0 following self-tests
    {
        // read PBIST_RGS and PBIST_RDS to identify the failure
        // in the PBIST_RAMT register (see TRM spnu499c Table 2-5)
        //tbd: report MCU self-test failure to error manager

        asm(" nop");
    }


    /*
    +--------------------------B-L-O-C-K---H-E-A-D-E-R------------------------+
    |                                                                         |
    |   Note: Resetting the PBIST controller after self-tests.                |
    |                                                                         |
    +-------------------------------------------------------------------------+
    */

    PBIST_PACT = 0x00000000;    // disable PBIST internal clock
    MSTGCR_bit.MSTGENA = 0x5;   // disable PBIST
}

After PBIST test on MCU SRAM, the contents of SRAM before the test will be completely lost, data or address stored in stack space are also lost. You must take care of data backup.

QJ,

So this have to be performed before jumping to main() ...

How about the same test on dual-port peripheral memories? Same?

Thanks. 

Thank you QJ. The PBIST code was moved to startup code before reaching main(), and it works now.  

Just for other people also looking to see the correct operation sequence, the following order shall be respected before reaching main():

1. HW auto-init on SRAM
2. PBIST on SRAM
3. Activation of ECC checking on SRAM

The system won't work is 1 and 2 are order-reversed.

Best regards,