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TMS570LS0432: What does this code mean

whong zhao
Genius 4190 points
Part Number: TMS570LS0432


Hello

 Team

  I want to  enable the ram ecc function， I use the safe library SL_Init_ECCTCRAM(...)

 Dose this function enable the RAM ecc function 

  • 0
    TI__Guru**** 199096 points

    Hello,

    Yes, you can use SL_Init_ECCTCRAM(...) to enable the RAM ECC. Since the SRAM ECC detection is enabled by default, you can use _SL_Init_ECCTCMRAM() to enable RAM ECC too.

  • 0 in reply to QJ Wang
    Genius 4190 points

    Hello

    Where explains that ECC is activated by default in the document.

     I saw that ECC needs to be re-enabled after reset.

    The certification company asked me to find evidence of whether ECC is normal.

  • 0 in reply to QJ Wang
    Genius 4190 points

    The SECDED logic inside the CPU is not enabled by default and must be enabled by the application. Writing 1 to bit 16 and bit 27 of Auxiliary Control Register to enable B0TCM and B1TCM ECC check (refer to ARM COrtex-R4 TRM). 

    Since the SRAM ECC detection is enabled by default

    What's the difference

  • 0 in reply to whong zhao
    TI__Guru**** 199096 points

    1. Writing 1 to bit 26 and bit 27 of Auxiliary Control Register enables SECDED logic inside the CPU.

    2. The CPU's event bus signals single-bit or multi-bit ECC error for TCRAM wrapper. These ECC error signals are monitored by the TCRAM. This monitoring is enabled by setting ECC_DETECT_EN to 0x5.

    If ECC is enabled in CPU core but disabled within TCRAM wrapper (ECC_DETECT_EN=0x5), the ECC error detected by CPU ECC logic will be ignored by TCRAM wrapper. 

  • 0 in reply to QJ Wang
    Genius 4190 points

    Hello

    Thank you

     the ECC error detected by CPU ECC logic,which trigger the ESM interrupt？？

  • +1 in reply to whong zhao
    TI__Guru**** 199096 points

    If ECC_DETECT_EN=0x05, ECC detect of SRAM wrapper is disabled. The SRAM ECC error will not exported to ESM and SRAM error status register. For 2-bit ECC error, data abort is generated, but ESM3.3 will not be set, and bit 5 of RAMERRSTATUS is not set.

    If ECC_DETECT_EN=0x0A, ECC detect of SRAM wrapper is enabled. The SRAM ECC error will exported to ESM and SRAM error status register. For 2-bit ECC error, data abort is generated, thet ESM3.3 will be set, and bit 5 of RAMERRSTATUS will be set too.