TM4C123BH6PM: How to transmit 0x0000 except for the TX data which is set?

Hi Kuerbis,

  I'm not very clear with your description. Is the buffer you are referring to the SPI FIFO or some type of ring buffer that you implement on the application. The SPI FIFO is only 8 location deep and you said you have configured for 9 buffers in the second case. I suppose it is a software buffer structure you implement on application, If not, please clarify. Do you have valid data in the TX FIFO when the slave receives the SPICLK from the master?

  If you are referring to the Transmit FIFO then there is below note on the datasheet. 

In slave mode, the SSI transmits data each time the master initiates a transaction. If the transmit
FIFO is empty and the master initiates, the slave transmits the 8th most recent value in the transmit
FIFO. If less than 8 values have been written to the transmit FIFO since the SSI module clock was
enabled using the Rn bit in the RCGCSSI register, then 0 is transmitted. Care should be taken to
ensure that valid data is in the FIFO as needed. The SSI can be configured to generate an interrupt
or a μDMA request when the FIFO is empty.

Hi Charles,

The customer is using uDAM. But they do the following program then also observe same behavior.

for(i=1; i < 9; i++){

       HWREG(SSI0_BASE + SSI_O_DR) = i;

   }

When the master provide clock, 0x0001 is transmitted after 9^th transaction.

What a kind of information do you need to investigate this?

Thank you for providing the information of Rn bit in the RCGCSSI register. This case is the slave generates the clock. Right? The customer case is the master provides the clock. So it’s the different case, isn’t it.

Thanks and Best regards,

Kuerbis

Hi Kuerbis,

  I'm unclear with your question now. In your original question, you were talking about the slave. It seems now you are talking about the master. Can you please clarify what is the problem. Is the MCU a SPI slave or a SPI master? If you are a master then you are generating the SPI clock. A slave does not generate SPI clock. Please clarify to me if the MCU is master or a slave first.

 I quoted the below statements from the datasheet. This is the behavior of the slave who is receiving the SPI clock from the master. Please read the below highlighted in red statement closely if it applies to you. Do you have enough data in the FIFO when the master sends you a clock? 

Charles Tsai said:

In slave mode, the SSI transmits data each time the master initiates a transaction. If the transmit
FIFO is empty and the master initiates, the slave transmits the 8th most recent value in the transmit
FIFO. If less than 8 values have been written to the transmit FIFO since the SSI module clock was
enabled using the Rn bit in the RCGCSSI register, then 0 is transmitted. Care should be taken to
ensure that valid data is in the FIFO as needed. The SSI can be configured to generate an interrupt
or a μDMA request when the FIFO is empty.

Hi Charles、

I’m talking about the slave.

I’m sorry that I got a wrong understanding about the Rn bit in the RCGCSSI register as the SPI clock generation. It’s just module clock enable and not SPI clock.

> Do you have enough data in the FIFO when the master sends you a clock? 

They write the data them the master start communication. So I think the enough data in the FIFO. But I’ll ask it.

The red statement is not matched with the customer reported. Do you have any idea?

Thanks and Best regards,

Kuerbis