TMS570LS3137: ESM Group1 DMA parity and DMA/DMM imprecise read error

Chuck Wong

Part Number: TMS570LS3137

Hello there,

In my application, the DMA module RAM was hardware auto-initialized during system startup (MSIENA_bit.MSIENA1 = 1), and the DMA parity check has been enabled with DMAPCR_bit.PARITY_ENA=0xA.

Following each DMA transfer for MibADC1 and MibSPI3, the ESM Group1 DMA parity error is declared (ESMSR1=0x00000008).

Following the CRC Engine Compression transfer, the ESM Group1 DMA parity error and DMA/DMM imprecise read error are declared (ESMSR1=0x00000028).

I've tried not activating the DMA RAM parity check, same behavior indicated by the ESMSR1 register.

Of course, this happens to more than one device.

Could you let me know where I should look at?

Thanks.

over 3 years ago

0 Chuck Wong over 3 years ago

Genius 3940 points

I just want to add that peripheral RAM auto-initialization and parity check were also enabled for the following peripherals, and without ESM issue encountered in the case of the DMA:

VIM
N2HET1
DCAN1
MIBADC1

0 QJ Wang over 3 years ago

TI__Guru**** 192146 points

Hello,

Is the DMA parity enabled before the DMA RAM is initialized? Otherwise, the parity RAM is not updated when performing DMA RAM auto-initialization.

Please take parity test by inserting a fault to DMA parity RAM. Test mode is entered by asserting the TEST bit in the Parity Control Register.

0 Chuck Wong over 3 years ago in reply to QJ Wang

Genius 3940 points

Hi QJ,

Yes I confirm that the ESM Group1 DMA parity error is gone after reversing the parity enabled and initialization sequence, thank you!

I've also reversed the said ordering for other devices, namely

VIM
N2HET1
DCAN1
MIBADC1

But the ESM Group1 DMA/DMM imprecision read error remains after 1 MB of Flash ROM has been compressed by the 64-bit CRC module. The DMA block transfer from Flash to CRC module is performed by DMA CH15, 4096 frames of 32 elements each, 64-bit read/write, auto-initiation disabled (so only one shot).

Any clue here?

Regards.

0 QJ Wang over 3 years ago in reply to Chuck Wong

TI__Guru**** 192146 points

The pattern counter is a 20-bit counter. To calculate CRC for >2MB memory region, please increase the CRC sector number

0 QJ Wang over 3 years ago in reply to QJ Wang

TI__Guru**** 192146 points

Please see my example of calculating CRC of a flash section which is > 1MB:

Pcount=1025 and Scount=128, so total size is 1025*128*8

int main(void)
{
/* USER CODE BEGIN (3) */
uint32_t i, abc;

abc = (uint32_t)flash_sector[3].start;

/* clear the ESM error manually */
esmREG->SR1[2] = 0x00000008U;
esmREG->SSR2 = 0x00000008U;
esmREG->EKR = 0x0000000A;
esmREG->EKR = 0x00000005;

//using CRC auto mode
crcInit();
_enable_IRQ();

//change to CRC semi-CPU mode
// crcREG->CTRL2 = (uint32)(CRC_SEMI_CPU);
crcREG->CTRL2 = (uint32)(CRC_FULL_CPU);
crcREG->SCOUNT_REG1= 1025;
crcREG->PCOUNT_REG1= 128; /*32 double-words*/

crcEnableNotification(crcREG,CRC_CH1_CC);

dma_config.SADD = (uint32_t)((uint32 *)0x00000000);
dma_config.DADD = (uint32_t)&(crcREG->PSA_SIGREGL1 );
dma_config.CHCTRL = 0;
dma_config.FRCNT = 128;
dma_config.ELCNT = 1025;

dma_config.ELDOFFSET = 0;
dma_config.ELSOFFSET = 0;
dma_config.FRDOFFSET = 0;
dma_config.FRSOFFSET = 0;
dma_config.PORTASGN = 4;
dma_config.RDSIZE = ACCESS_64_BIT;
dma_config.WRSIZE = ACCESS_64_BIT;
dma_config.TTYPE = BLOCK_TRANSFER;
dma_config.ADDMODERD = ADDR_INC1;
dma_config.ADDMODEWR = ADDR_FIXED;
dma_config.AUTOINIT = AUTOINIT_OFF;

// setting dma control packets for receive
dmaSetCtrlPacket(DMA_CH0, dma_config);
dmaReqAssign(DMA_CH0, 26); //DMA request line 26, CRC1 channel0
dmaSetChEnable(DMA_CH0, DMA_SW);

dmaEnable();

//delay
for(i=0; i<0x100000; i++);

if ((CRC0_Test[0] == CRC0_Ref[0]) && (CRC0_Test[1] == CRC0_Ref[1]))
{
CRC0_Error = 0;
} else{
CRC0_Error = 1;
}

while(1);
/* USER CODE END */

return 0;
}

0 Chuck Wong over 3 years ago in reply to QJ Wang

Genius 3940 points

QJ Wang said:
The pattern counter is a 20-bit counter. To calculate CRC for >2MB memory region, please increase the CRC sector number

No problem here, I'm just trying to compute the CRC of 1 MB of Flash ROM, so pattern count=4096 and sector count=32 to make up 4096*32*8=1 MB.

DMA imprecise read must be related to something else, but I don't seem to be able to locate the full explanation of this ESM Group1 error. Maybe you can point me to it in the TRM or device data sheet?

0 Chuck Wong over 3 years ago in reply to QJ Wang

Genius 3940 points

QJ Wang said:
dma_config.FRCNT = 128;
dma_config.ELCNT = 1025;

In accordance to your comments, the FRCNT should be 1025 and ELCNT should be 128 for a total of 1MB+128*8-byte sector.

In my case, I've modified both the CRC register to FRCNT=1024 and ELCNT=128 (rather than 4096 and 32 respectively) to obtain again 1MB, but the same "DMA imprecise read" ESM Group1 error remain.

The source of the error might be something else ...

Thanks.

0 Chuck Wong over 3 years ago in reply to QJ Wang

Genius 3940 points

QJ Wang said:
crcREG->SCOUNT_REG1= 1025;
crcREG->PCOUNT_REG1= 128; /*32 double-words*/

Of course, with regards to my last post, those numbers also need to be exchanged.

0 QJ Wang over 3 years ago in reply to Chuck Wong

TI__Guru**** 192146 points

I did a test with sector size = 1025. The DMA transfer is triggered using RTI timer. I remember I posted this test code, but couldn't find it. I will post again.

0 QJ Wang over 3 years ago in reply to QJ Wang

TI__Guru**** 192146 points

sys_link.cmd

sys_main.c

/** @file sys_main.c 
*   @brief Application main file
*   @date 11-Dec-2018
*   @version 04.07.01
*
*   This file contains an empty main function,
*   which can be used for the application.
*/

/* 
* Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com 
* 
* 
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*  are met:
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*    notice, this list of conditions and the following disclaimer in the 
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*  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 
*  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*/


/* USER CODE BEGIN (0) */
/* USER CODE END */

/* Include Files */

#include "sys_common.h"

/* USER CODE BEGIN (1) */
#include "crc.h"
#include "sys_dma.h"
#include "esm.h"
#include "rti.h"
#include "gio.h"
#include "het.h"
/* USER CODE END */

/** @fn void main(void)
*   @brief Application main function
*   @note This function is empty by default.
*
*   This function is called after startup.
*   The user can use this function to implement the application.
*/

/* Place const to memory location around 1MB */
/* USER CODE BEGIN (2) */
typedef struct Sectors
{ void * start;
  unsigned int length;       // number of 32-bit words
  unsigned int bankNumber;
  unsigned int sectorNumber;
  unsigned int FlashBaseAddress;
} SECTORS;

typedef struct Banks
{ void * start;
  unsigned int length;  // number of 32-bit words
  unsigned int bankNumber;
  unsigned int FlashBaseAddress;
  unsigned int numOfSectors;
} BANKS;

#define NUMBEROFSECTORS 108
const SECTORS flash_sector[NUMBEROFSECTORS]=
{
  (void *)0x00000000, 0x08000, 0,  0, 0xfff87000,
  (void *)0x00008000, 0x08000, 0,  1, 0xfff87000,
  (void *)0x00010000, 0x08000, 0,  2, 0xfff87000,
  (void *)0x00018000, 0x08000, 0,  3, 0xfff87000,
  (void *)0x00020000, 0x20000, 0,  4, 0xfff87000,
  (void *)0x00040000, 0x20000, 0,  5, 0xfff87000,
  (void *)0x00060000, 0x20000, 0,  6, 0xfff87000,
  (void *)0x00080000, 0x20000, 0,  7, 0xfff87000,
  (void *)0x000A0000, 0x20000, 0,  8, 0xfff87000,
  (void *)0x000C0000, 0x20000, 0,  9, 0xfff87000,
  (void *)0x000E0000, 0x20000, 0, 10, 0xfff87000,
  (void *)0x00100000, 0x20000, 0, 11, 0xfff87000,
  (void *)0x00120000, 0x20000, 0, 12, 0xfff87000,
  (void *)0x00140000, 0x20000, 0, 13, 0xfff87000,
  (void *)0x00160000, 0x20000, 0, 14, 0xfff87000,
  (void *)0x00180000, 0x20000, 1,  0, 0xfff87000,
  (void *)0x001A0000, 0x20000, 1,  1, 0xfff87000,
  (void *)0x001C0000, 0x20000, 1,  2, 0xfff87000,
  (void *)0x001E0000, 0x20000, 1,  3, 0xfff87000,
  (void *)0x00200000, 0x20000, 1,  4, 0xfff87000,
  (void *)0x00220000, 0x20000, 1,  5, 0xfff87000,
  (void *)0x00240000, 0x20000, 1,  6, 0xfff87000,
  (void *)0x00260000, 0x20000, 1,  7, 0xfff87000,
  (void *)0x00280000, 0x20000, 1,  8, 0xfff87000,
  (void *)0x002A0000, 0x20000, 1,  9, 0xfff87000,
  (void *)0x002C0000, 0x20000, 1, 10, 0xfff87000,
  (void *)0x002E0000, 0x20000, 1, 11, 0xfff87000,

  (void *)0x00000000, 0x08000, 0,  0, 0xfff87000,
  (void *)0x00008000, 0x08000, 0,  1, 0xfff87000,
  (void *)0x00010000, 0x08000, 0,  2, 0xfff87000,
  (void *)0x00018000, 0x08000, 0,  3, 0xfff87000,
  (void *)0x00020000, 0x20000, 0,  4, 0xfff87000,
  (void *)0x00040000, 0x20000, 0,  5, 0xfff87000,
  (void *)0x00060000, 0x20000, 0,  6, 0xfff87000,
  (void *)0x00080000, 0x20000, 0,  7, 0xfff87000,
  (void *)0x000A0000, 0x20000, 0,  8, 0xfff87000,
  (void *)0x000C0000, 0x20000, 0,  9, 0xfff87000,
  (void *)0x000E0000, 0x20000, 0, 10, 0xfff87000,
  (void *)0x00100000, 0x20000, 0, 11, 0xfff87000,
  (void *)0x00120000, 0x20000, 0, 12, 0xfff87000,
  (void *)0x00140000, 0x20000, 0, 13, 0xfff87000,
  (void *)0x00160000, 0x20000, 0, 14, 0xfff87000,
  (void *)0x00180000, 0x20000, 1,  0, 0xfff87000,
  (void *)0x001A0000, 0x20000, 1,  1, 0xfff87000,
  (void *)0x001C0000, 0x20000, 1,  2, 0xfff87000,
  (void *)0x001E0000, 0x20000, 1,  3, 0xfff87000,
  (void *)0x00200000, 0x20000, 1,  4, 0xfff87000,
  (void *)0x00220000, 0x20000, 1,  5, 0xfff87000,
  (void *)0x00240000, 0x20000, 1,  6, 0xfff87000,
  (void *)0x00260000, 0x20000, 1,  7, 0xfff87000,
  (void *)0x00280000, 0x20000, 1,  8, 0xfff87000,
  (void *)0x002A0000, 0x20000, 1,  9, 0xfff87000,
  (void *)0x002C0000, 0x20000, 1, 10, 0xfff87000,
  (void *)0x002E0000, 0x20000, 1, 11, 0xfff87000,

  (void *)0x00000000, 0x08000, 0,  0, 0xfff87000,
  (void *)0x00008000, 0x08000, 0,  1, 0xfff87000,
  (void *)0x00010000, 0x08000, 0,  2, 0xfff87000,
  (void *)0x00018000, 0x08000, 0,  3, 0xfff87000,
  (void *)0x00020000, 0x20000, 0,  4, 0xfff87000,
  (void *)0x00040000, 0x20000, 0,  5, 0xfff87000,
  (void *)0x00060000, 0x20000, 0,  6, 0xfff87000,
  (void *)0x00080000, 0x20000, 0,  7, 0xfff87000,
  (void *)0x000A0000, 0x20000, 0,  8, 0xfff87000,
  (void *)0x000C0000, 0x20000, 0,  9, 0xfff87000,
  (void *)0x000E0000, 0x20000, 0, 10, 0xfff87000,
  (void *)0x00100000, 0x20000, 0, 11, 0xfff87000,
  (void *)0x00120000, 0x20000, 0, 12, 0xfff87000,
  (void *)0x00140000, 0x20000, 0, 13, 0xfff87000,
  (void *)0x00160000, 0x20000, 0, 14, 0xfff87000,
  (void *)0x00180000, 0x20000, 1,  0, 0xfff87000,
  (void *)0x001A0000, 0x20000, 1,  1, 0xfff87000,
  (void *)0x001C0000, 0x20000, 1,  2, 0xfff87000,
  (void *)0x001E0000, 0x20000, 1,  3, 0xfff87000,
  (void *)0x00200000, 0x20000, 1,  4, 0xfff87000,
  (void *)0x00220000, 0x20000, 1,  5, 0xfff87000,
  (void *)0x00240000, 0x20000, 1,  6, 0xfff87000,
  (void *)0x00260000, 0x20000, 1,  7, 0xfff87000,
  (void *)0x00280000, 0x20000, 1,  8, 0xfff87000,
  (void *)0x002A0000, 0x20000, 1,  9, 0xfff87000,
  (void *)0x002C0000, 0x20000, 1, 10, 0xfff87000,
  (void *)0x002E0000, 0x20000, 1, 11, 0xfff87000,

  (void *)0x00000000, 0x08000, 0,  0, 0xfff87000,
  (void *)0x00008000, 0x08000, 0,  1, 0xfff87000,
  (void *)0x00010000, 0x08000, 0,  2, 0xfff87000,
  (void *)0x00018000, 0x08000, 0,  3, 0xfff87000,
  (void *)0x00020000, 0x20000, 0,  4, 0xfff87000,
  (void *)0x00040000, 0x20000, 0,  5, 0xfff87000,
  (void *)0x00060000, 0x20000, 0,  6, 0xfff87000,
  (void *)0x00080000, 0x20000, 0,  7, 0xfff87000,
  (void *)0x000A0000, 0x20000, 0,  8, 0xfff87000,
  (void *)0x000C0000, 0x20000, 0,  9, 0xfff87000,
  (void *)0x000E0000, 0x20000, 0, 10, 0xfff87000,
  (void *)0x00100000, 0x20000, 0, 11, 0xfff87000,
  (void *)0x00120000, 0x20000, 0, 12, 0xfff87000,
  (void *)0x00140000, 0x20000, 0, 13, 0xfff87000,
  (void *)0x00160000, 0x20000, 0, 14, 0xfff87000,
  (void *)0x00180000, 0x20000, 1,  0, 0xfff87000,
  (void *)0x001A0000, 0x20000, 1,  1, 0xfff87000,
  (void *)0x001C0000, 0x20000, 1,  2, 0xfff87000,
  (void *)0x001E0000, 0x20000, 1,  3, 0xfff87000,
  (void *)0x00200000, 0x20000, 1,  4, 0xfff87000,
  (void *)0x00220000, 0x20000, 1,  5, 0xfff87000,
  (void *)0x00240000, 0x20000, 1,  6, 0xfff87000,
  (void *)0x00260000, 0x20000, 1,  7, 0xfff87000,
  (void *)0x00280000, 0x20000, 1,  8, 0xfff87000,
  (void *)0x002A0000, 0x20000, 1,  9, 0xfff87000,
  (void *)0x002C0000, 0x20000, 1, 10, 0xfff87000,
  (void *)0x002E0000, 0x20000, 1, 11, 0xfff87000

};

#define NUMBEROFBANKS 2
const BANKS flash_bank[NUMBEROFBANKS]=
{
  (void *) 0x00000000, 0x180000, 0, 0xfff87000, 15,
  (void *) 0x00180000, 0x180000, 1, 0xfff87000, 12,
};

g_dmaCTRL dma_config;    // dma control packet configuration stack

unsigned int  CRC0_Test[2];
unsigned int CRC0_Error, CRC1_Error;
const unsigned int CRC0_Ref[2] = {0xF1F3BC95, 0xE050554A};

unsigned int countSector = 0;
unsigned int COMPRESSION_COMPLETE_FLAG = 0x5555AAAA;
/* USER CODE END */

int main(void)
{
/* USER CODE BEGIN (3) */
    uint32_t i, abc;

    abc = (uint32_t)flash_sector[3].start;

    /* clear the ESM error manually */
    esmREG->SR1[2] = 0xFFFFFFFFU;
    esmREG->SSR2   = 0xFFFFFFFFU;
    esmREG->EKR = 0x0000000A;
    esmREG->EKR = 0x00000000;

    //using CRC auto mode
    crcInit();

    /* Initialize RTI driver */
    rtiInit();

    /* Set high end timer GIO port hetPort pin direction to all output */
    gioSetDirection(hetPORT1, 0xFFFFFFFF);

    /* Enable RTI Compare 0 interrupt notification */
    rtiEnableNotification(rtiNOTIFICATION_COMPARE0);

    /*Enable RTI DMA 0*/
    rtiREG1->SETINTENA   = 0x1 << 8;  //Set compare DMA request 0.

    /* Enable IRQ - Clear I flag in CPS register */
    /* Note: This is usually done by the OS or in an svc dispatcher */
    _enable_IRQ();

    //change to CRC semi-CPU mode
    crcREG->CTRL2 = (uint32)(CRC_SEMI_CPU);
    crcREG->SCOUNT_REG1= 1025;
    crcREG->PCOUNT_REG1= 128; /*32 double-words*/

    /*Enable CRC CH1 compression complete interrupt*/
    crcEnableNotification(crcREG, CRC_CH1_CC);

    dma_config.SADD = (uint32_t)((uint32 *)0x00000000);
    dma_config.DADD = (uint32_t)&(crcREG->PSA_SIGREGL1 );
    dma_config.CHCTRL = 0;
    dma_config.FRCNT  = 1025;
    dma_config.ELCNT  = 128;

    dma_config.ELDOFFSET = 0;
    dma_config.ELSOFFSET = 0;
    dma_config.FRDOFFSET = 0;
    dma_config.FRSOFFSET = 0;
    dma_config.PORTASGN  = 4;
    dma_config.RDSIZE    = ACCESS_64_BIT;
    dma_config.WRSIZE    = ACCESS_64_BIT;
    dma_config.TTYPE     = FRAME_TRANSFER;
    dma_config.ADDMODERD = ADDR_INC1;
    dma_config.ADDMODEWR = ADDR_FIXED;
    dma_config.AUTOINIT  = AUTOINIT_OFF;

    // setting dma control packets for receive
    dmaSetCtrlPacket(DMA_CH0, dma_config);
    dmaReqAssign(DMA_CH0, 12);   //DMA request line 12, The request is generate dby RTI CMP0, CRC1 channel0
    dmaSetChEnable(DMA_CH0, DMA_HW);

    /* Enable Block Transfer Complete interrupt for the receive after transfer complete */
    dmaEnableInterrupt(DMA_CH0, FTC);
    dmaEnableInterrupt(DMA_CH0, BTC);

    dmaEnable();

    /* Start RTI Counter Block 0 */
    rtiStartCounter(rtiCOUNTER_BLOCK0);

    //wait for completion
    while(COMPRESSION_COMPLETE_FLAG != 0x5A5A5A5A);

    if ((CRC0_Test[0] == CRC0_Ref[0]) && (CRC0_Test[1] == CRC0_Ref[1]))
    {
        CRC0_Error = 0;
    } else{
        CRC0_Error = 1;
    }

    while(1);
/* USER CODE END */

    return 0;
}


/* USER CODE BEGIN (4) */
void crcNotification(crcBASE_t *crc, uint32 flags)
{
    if (flags == CRC_CH1_CC){    //Ch1 Compression Complete
        CRC0_Test[0] = crc->PSA_SECSIGREGL1;
        CRC0_Test[1] = crc->PSA_SECSIGREGH1;
    }
}

void rtiNotification(uint32 notification)
{
/*  enter user code between the USER CODE BEGIN and USER CODE END. */
    /* Toggle HET pin 0 */
    gioSetPort(hetPORT1, gioGetPort(hetPORT1) ^ 0x00000001);
}

void dmaGroupANotification(dmaInterrupt_t inttype, uint32 channel)
{
    if ( inttype == FTC){
      asm("  nop");
      countSector++;
    }
    if ( inttype == BTC)
    {
      asm("  nop");
      COMPRESSION_COMPLETE_FLAG = 0x5A5A5A5A;
    }

}
/* USER CODE END */

0 QJ Wang over 3 years ago in reply to QJ Wang

TI__Guru**** 192146 points

In the linker cmd file, the const is allocated to a flash area which cross the 1MB.

0 Chuck Wong over 3 years ago in reply to QJ Wang

Genius 3940 points

Hi QJ,

My case is only 1MB, so I don't need to go with 1025 frames, 1024 frames of 128 elements of 8 bytes makes up nicely 1 MB, so the issue is not there. Beside that, I also use the RTI to trigger the transfer and every time it succeeds, I may confirm that the CRC is correctly computed because even if I change only one single bit in my binary code, the CRC changes.

My issue is that at the end of each CRC compression completion, the ESM Group1 error "DMA/DMM imprecise error" was signaled.

Thanks.

0 QJ Wang over 3 years ago in reply to Chuck Wong

TI__Guru**** 192146 points

Hi Wong,

This error (ESM 1.5 or ESM 1.13) might be caused by illegal memory address.

I don't see this kind of error using my code posted days ago:

CRC: 1025 sectors.

ESM: stat1=0x0

0 Chuck Wong over 3 years ago in reply to QJ Wang

Genius 3940 points

This is strange ...

I've tried various things, including by triggering the DMA manually, setting the DMA AIM bit (for auto-initiation ON) rather than one shot, but to no avail.

When I set the AIM bit and trigger the DMA only manually by using the DMASWCHENAS register, as soon as the first transfer took place, the "DMA/DMM imprecise read error" is permanent and I could not reset it manually by writing directly using ESMSR1=0x00000020 (i.e. the error bit is always set even DMA not triggered but I was able to clear the error bit using ESMSR1= command previously when the AIM bit was 0).

Any clue here?

Because of the Thanksgiving holiday in the U.S., TI E2E™ design support forum responses may be delayed from November 25 through December 2. Thank you for your patience.

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TMS570LS3137: ESM Group1 DMA parity and DMA/DMM imprecise read error