TMS570LS3137: N2Het read issue when reading back programm and control field

Hi Philipp,

The NHET RAM is implemented as 4 banks with two ports RAM. CPU and NHET use different ports to access (read and write) the NHET RAM. NHET accesses NHET RAM has higher priority than accesses from CPU.

The consecutive read of a control field and a data field of the same instruction performed by CPU is always done as a simultaneous 64- bit read access. This means that at the same time control field is read, data field is loaded in a shadow register. So the second access will read data field from the shadow register instead of the N2HET RAM. 

The NHET instruction has an option allowing to automatically clear the data field immediately after the data field is read by the external host CPU. This option is set by writing 1 to bit 26 of the control field. CPU reading an data field of instruction from NHET RAM doesn't impact the data field if the automatic read-clear option of the instruction is not set.

Hi,

something like this is what we expected, however, this is still not clear to us. Each instruction consists of 128 bit. The first 32 bit are the program word, the second are the control word, the third are the data word and the last 32 bits are reserved. We first read the program word and afterwards the control word. As far as I understand between the RAM and the CPU is some kind of register/buffer where this data is loaded into in chunks of 64 bits, However, this would mean that by reading the program word the control word is also loaded. Therefore, when reading the control word no new load should happen, as it is already available in the register and hence, the data word should not be loaded at all right? If the control word is newly loaded (64-bit including the data word), this would in my understanding imply that the data word would be newly loaded as well on reading as the control word was also newly loaded even though it already existed in the shadow register, hence, this error should not occur.

General context: We use in total three instructions: 1) CNT, 2) ECNT & 3) ECNT. When we perform the checking of the program and control word in the following order: 1-CNT, 2-ECNT, 3-ECNT and aftwards read the data word in the following order 1-CNT, 2-ECNT, 3-ECNT everything seems fine. However, if we do the following data word reading, we get the described problem: 3-ECNT, 2-ECNT, 1-CNT. (Same is true for any kind of mixing, as long as the last read program and control word also the data word is read right after). So our main question that we need to understand is, that no such problem can occur, if we use the descibed order (read back 1, 2, 3 - read data 1, 2, 3).

Using the automatic clear is not an option for us.

It would be really great to get more insight on this topic, as this is a key feature of out system.

Best regards,
Philipp

Hi Philipp,

Thanks for providing more details.

The 64-bit read is only applied to the consecutive read of control field and data field of the same instruction. In your case, reading 3-ECNT control word + reading 3-ECNT data word is 64-bit read access. When CPU reads 3-ECNT control field, it will load the data field to a shadow register simultaneously. Later when CPU reads 3-ECNT data filed, CPU will read the data field from the shadow register rather than from NHET RAM.

Hi,

Thank you for that explanation. That is quite interesting and unexpected. Just had a look at the manual "TMS570LS31x/21x 16/32-Bit RISC Flash Microcontroller Technical Reference Manual" again at section 20.2.4.2 "64-bit Read Access", which is what you basically explained. There it says "The consecutive read of a control field CF(n) and a data field DF(n) of the same instruction (n) performed by the same master (for example, CPU, DMA, or any other master) is always done as a simultaneous 64- bit read access." Does this imply that 64-bit read access only happens if I got these two instructions one after another in my code (magically performed by the compiler) or does that mean that every time we read the control field or data field, a 64-bit read access is perfromed? If the latter is the case, how large is this shadow register and when will it be deleted / updated? In 20.2.4.2 it says that there are three shadow registers that in order to make reading by different masters possible. However, does that mean that each master only uses one shadow register or can one master use multiple shadow registers?

We need to make sure that our data is up to date.

Best regards,

Philipp

Hello,

perfect thank you that solves our problem! By reading CF and then PF (instead of PF and then CF) in the self test, we can get around this issue. After knowing how thinks work one realizes that this is actually in the manual. But maybe a warning box would be nice for future users that they don't run into the same issue? 

Thanks for your help,

Philipp