Hello Team,
I'm trying to implement ECC checking mechanism for Interrupt Vector Table ECC Testing. By manual insertion of faults in ECC bits and check the ESM functionality mentioned in TRM as below
The following sequence should be used for injecting faults to data bits and testing the ECC check feature.
1. Write the data locations of VIM RAM with the required patterns while keeping ECCENA active. The
ECC bits will be automatically initialized along with data bits.
2. Disable ECC by setting ECCENA=0 in ECCCTRL register. In this mode, writing to data bits does not
automatically update ECC bits.
3. In this mode, it is possible to corrupt data bits using any of the following methods.
• Read the data bits, flip one bit and write back
• Read the data bits, flip 2 bits and write back
4. Depending on the kind of corruption created, read back the data bits and check for the correction error
(single-bit error or double-bit error or no error).
5. Read the UERRADDR and SBERRADDR registers and check for the correct address capture as well.
Questions:
- What is the meaning of the required pattern in the first point and how is the data location chosen? Please provide an example
- How to read and write the data bits done? is it done using any register?
I'm stuck at these points.Kindly see the below code
/* USER CODE BEGIN (0) */
/* USER CODE END */
/* Include Files */
#include "HL_sys_common.h"
/* USER CODE BEGIN (1) */
#include "HL_reg_vim.h"
#include "HL_esm.h"
#include "HL_gio.h"
#include "HL_reg_esm.h"
#include "HL_sys_vim.h"
#include "HL_system.h"
/* USER CODE END */
/** @fn void main(void)
* @brief Application main function
* @note This function is empty by default.
*
* This function is called after startup.
* The user can use this function to implement the application.
*/
/* USER CODE BEGIN (2) */
#define VIM_CHANNEL 20U
#define vimRAM ((vimRAM_t *)0xFFF82000U)
/* USER CODE END */
int main(void)
{
/* USER CODE BEGIN (3) */
uint32 index_value;
uint32 channel_address;
esmInit();
vimInit();
//esmGroup1Notification(esmREG,esmREG->SR1[2]);
vimREG->ECCCTL = (uint32)((uint32)0xA << 0U | /* VIM ECC is enabled */
(uint32)0x5 << 8 | /* Enable memory-mapping of ECC bits for read/write operation */
(uint32)0xA << 16 | /* Enable correction of SBE detected by the SECDED block */
(uint32)0xA << 24); /* Enable Error Event upon detection of SBE the Interrupt Vector Table */
//Result after bitwise operation : 1010 0000 1010 0000 0101 0000 1010
//Read 32 bit volatile register
index_value = vimREG->IRQINDEX;