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TMS570LC4357: VIM ECC check

Part Number:

Hello Team,

I'm trying to implement ECC checking mechanism for Interrupt Vector Table ECC Testing. By manual insertion of faults in ECC bits and check the ESM functionality mentioned in TRM as below

The following sequence should be used for injecting faults to data bits and testing the ECC check feature.
1. Write the data locations of VIM RAM with the required patterns while keeping ECCENA active. The
ECC bits will be automatically initialized along with data bits.
2. Disable ECC by setting ECCENA=0 in ECCCTRL register. In this mode, writing to data bits does not
automatically update ECC bits.
3. In this mode, it is possible to corrupt data bits using any of the following methods.
• Read the data bits, flip one bit and write back
• Read the data bits, flip 2 bits and write back
4. Depending on the kind of corruption created, read back the data bits and check for the correction error
(single-bit error or double-bit error or no error).
5. Read the UERRADDR and SBERRADDR registers and check for the correct address capture as well.

 

Questions:

  1. What is the meaning of the required pattern in the first point and how is the data location chosen? Please provide an example
  2. How to read and write the data bits done? is it done using any register?

I'm stuck at these points.Kindly see the below code 

 

/* USER CODE BEGIN (0) */
/* USER CODE END */

/* Include Files */

#include "HL_sys_common.h"

/* USER CODE BEGIN (1) */
#include "HL_reg_vim.h"
#include "HL_esm.h"
#include "HL_gio.h"
#include "HL_reg_esm.h"
#include "HL_sys_vim.h"
#include "HL_system.h"
/* USER CODE END */


/** @fn void main(void)
 *   @brief Application main function
 *   @note This function is empty by default.
 *
 *   This function is called after startup.
 *   The user can use this function to implement the application.
 */

/* USER CODE BEGIN (2) */
#define VIM_CHANNEL 20U
#define vimRAM ((vimRAM_t *)0xFFF82000U)

/* USER CODE END */

int main(void)
{
    /* USER CODE BEGIN (3) */

    uint32 index_value;
    uint32 channel_address;

    esmInit();
    vimInit();

    //esmGroup1Notification(esmREG,esmREG->SR1[2]);


    vimREG->ECCCTL = (uint32)((uint32)0xA << 0U | /* VIM ECC is enabled */
                     (uint32)0x5 << 8 |           /* Enable memory-mapping of ECC bits for read/write operation */
                     (uint32)0xA << 16 |          /* Enable correction of SBE detected by the SECDED block */
                     (uint32)0xA << 24);          /* Enable Error Event upon detection of SBE the Interrupt Vector Table */
                     //Result after bitwise operation : 1010 0000 1010 0000 0101 0000 1010

    //Read 32 bit volatile register
     index_value = vimREG->IRQINDEX;

  • 1. The data written to vector table should be a valid the memory address. It is better to use a address of a dummy interrupt handler. If you use the HALCOGen generated code, the VIM vector table is already initialized in vimInit(). The address in most of the locations in vector table points to phantomInterrupt(void).

    2. Read/write the data directly from/to the memory location

        data =  (*(volatile uint32 *)0xFFF82000U        --> read first word from VIM vector table

        ecc =  (*(volatile uint32 *)0xFFF82400U        --> read first data from ECC space

        You can flip one bit in ECC value:

        ecc ^= 0x1U;

  • 1. The data written to vector table should be a valid the memory address. It is better to use a address of a dummy interrupt handler. If you use the HALCOGen generated code, the VIM vector table is already initialized in vimInit(). The address in most of the locations in vector table points to phantomInterrupt(void).

    2. Read/write the data directly from/to the memory location

        data =  (*(volatile uint32 *)0xFFF82000U        --> read first word from VIM vector table

        ecc =  (*(volatile uint32 *)0xFFF82400U        --> read first data from ECC space

        You can flip one bit in ECC value:

        ecc ^= 0x1U;

  • Thank you for the feedback. 

    My project has a requirement to check ECC for RAM, flash, and most of the modules. Does RAM ECC also have the same steps? which module can I refer to in TMS?

  • Yes, you can use the same way to test RAM ECC.

  • I have tried to implement the ram ECC logic by referring to TRM.

    In the TRM there is mention of RAMOCCUR and programming of single-bit error correction threshold in section 8.2.5 Emulation/Debug Mode Behavior. But there is no register available to do so. 

    Parallelly I have referred to the function checkRAMECC() from the Part Number: TMS570LS3137where there are registers like RAMOCCUR , RAMTHRESHOLD, and RAMINTCTRL.

    Also, it is mentioned that  ->The L2RAMW or ECC address that caused the fault is captured in the RAMUERRADDR register. But there is no such register available in the TRM under the L2RAMW Module registers listed in Table 8-2

    1. Are these registers not required for the RAM ECC implementation of Part Number: TMS570LC4357?
    2.Which are the registers I have to use for the same to do implementation in TMS570LC4357?
    3. What are configuration needed in halcogen?
    4. Can you briefly explain the steps I have to do for the ram ECC check?
  • Hello,

    RAMUERRADDR and RAMOCCUR are not used in TMS570LC43x device. Those two registers are available only on TMS570LSx and RM4x device.

    For TMS570LC43x, the ECC is enabled by default , and can not be disabled. So you can't simply turn off ECC then create a mismatch. There is an alternative method to allow you to write directly to the ECC memory and create the corruption in this way.

  • Hello,

    WHich is the alternative way to generate the mismatch? in the chapter L2RAMW, there are no steps provided. Can you provide the steps or mention the chapter to refer

  • Hello,

    The RAM ECC memory starts at 0x08400000. The ECC memory can be directly accessed via the memory-mapped offset addresses.  Writes to ECC memory must be 64-bit aligned.

    To write to RAM ECC memory, the 8th bit of RAM control register (RAMCTRL) must be set:

        l2ramwREG->RAMCTRL |= 1 << 8;

    If a single-bit ECC error occurs, no ESM flag is set. The error address is stored in EPC content register. 

    For example

    1. The original content in RAM location 0x08004000 is 0x1234567812345678, and the ECC value at 0x08404000 is 0x8D

    2. enable ECC write:  l2ramwREG->RAMCTRL |= 1 << 8;

    3. Flip one bit of ECC value by writing 0x8c8c8c8c8c8c8c8c to 0x08404000 

    4. Read 0x08004000. The single-bit ECC error is generated and data is corrected.

        

    The EPC registers: Byte 0 of CAM index 0 shows the entry 0 is occupied, and CAM Content 0 is the error address

  • The SECDED compare logic can be tested using test mode. The test mode is enabled by writing 0xA to RAMTEST register. The data vectors and ECC are programmed to DIAG_DATA_VECTOR and DIAG_ECC.

    Please refer to section 8.2.6 of TRM.

    First single-bit ECC error, the bit 19 and 21 of RAMERRSTATUS register are set 

    First 2-bit ECC error, the bit 20 and 22 of RAMERRSTATUS register are set 

    The following is the example code:

    /* 1-bit ECC error */
    /* write value to test vectors*/
    l2ramwREG->DIAGDATAVECTOR_L = 0x00000000;
    l2ramwREG->DIAGDATAVECTOR_H = 0x00000000;
    l2ramwREG->DIAG_ECC = 0x0D; //the correct ECC is 0x0C

    /* Enable Test mode*/
    l2ramwREG->RAMTEST = (2 << 6) | (0xa << 0);

    /* Trigger Test*/
    l2ramwREG->RAMTEST = (1 << 8);

    /* 2-bit ECC error */
    /* write value to test vectors*/
    l2ramwREG->DIAGDATAVECTOR_L = 0x00000000;
    l2ramwREG->DIAGDATAVECTOR_H = 0x00000000;
    l2ramwREG->DIAG_ECC = 0x0F;

    /* Enable Test mode*/
    l2ramwREG->RAMTEST = (2 << 6) | (0xa << 0);
    /* Trigger Test*/
    l2ramwREG->RAMTEST = (1 << 8);

  • Hi Wang,

    Is the RAM ECC single-bit error reported to ESM?

    Is Group3 channel 3 used for L2RAMW - double-bit ECC uncorrectable error? Can you please share the steps to perform this ?

  • If there is one bit ECC error when writing data to SRAM, the error will be reported to ESM group 1 (1.26).