HALCOGEN: HalCoGen generates sys_pmu.asm with missing asm instructions for TMS5701227

v01d

Expert 2025 points

Part Number: HALCOGEN

HalCogen generates /provides automatically its HAL layer and, for odd reason it generated me buggy / missing asm for 1227 only, and not for 0714 or 0914.
(Just retested by deleting this asm file, and generating again)

This is for the set/ get event counters. What it generated for 1227 is :

;-------------------------------------------------------------------------------
; Set Count event
; SourceId : PMU_SourceId_009
; DesignId : PMU_DesignId_009
; Requirements : HL_SR485

    .def     _pmuSetCountEvent_
    .asmfunc

_pmuSetCountEvent_

        mcr   p15, #0, r0, c9, c12, #5 ; select counter
        mcr   p15, #0, r1, c9, c13, #1 ; select event
        bx    lr

    .endasmfunc

;-------------------------------------------------------------------------------
; Get Event Counter Count Value
; SourceId : PMU_SourceId_011
; DesignId : PMU_DesignId_011
; Requirements : HL_SR486

    .def     _pmuGetEventCount_
    .asmfunc

_pmuGetEventCount_

        mcr   p15, #0, r0, c9, c12, #5 ; select counter
        mrc   p15, #0, r0, c9, c13, #2 ; read event counter
        bx    lr

This kinda has off-by-one on the event counter selection, it' missing

 lsr r0, r0, #1

as the first line for those calls. And, oddly , it does insert it for 0714 & 0914 code... Don't know whats up with my 1227 config

.tms570_ls1227_zwt_.tar

over 4 years ago

0 QJ Wang over 4 years ago

TI__Guru**** 196776 points

Hi,

There is not problem with this function. When calling this function, two function arguments should be provided, one is r0 and other is r1.

To use counter 0, r0=0x0; to use counter 1, r0=0x1; and to use counter 2, r0=0x2

r1 is used to select the event number

Please refer to ARM COrtex-R4 TRM.

Here is my example of using PMU:

http://software-dl.ti.com/hercules/hercules_docs/latest/hercules/Examples/Examples.html#using-performance-monitoring-unit-pmu-to-evaluate-code-efficiency

0 v01d over 4 years ago in reply to QJ Wang

Expert 2025 points

QJ Wang

You NEEED to first have a look at the TI HalCoGen's provided API :

/** @fn void _pmuSetCountEvent_(uint32 counter, uint32 event)
*   @brief Set event counter count event
*   @param[in] counter - Counter select 0..2
*   @param[in] event   - Count event
*/
void _pmuSetCountEvent_(uint32 counter, uint32 event);

/** @fn uint32 _pmuGetCycleCount_(void)
*   @brief Returns current cycle counter value
*
*   @return cycle count.
*/

uint32 _pmuGetEventCount_(uint32 counter);

/** @fn uint32 _pmuGetOverflow_(void)
*   @brief Returns current overflow register and clear flags
*
*   @return overflow flags.
*/

Specifically at uint32 _pmuGetEventCount_(uint32 counter);.

May be also review TI"s app note / report called "Execution Time Measurement for Hercules ARM® Safety
MCUs".

After that, may be bounce me to the ARM's TRM. ( Or fix the API )

0 v01d over 4 years ago in reply to QJ Wang

Expert 2025 points

QJ Wang said:
There is not problem with this function. When calling this function, two function arguments should be provided, one is r0 and other is r1.

Have you looked at the link you provided me?

...
event0_cycles = _pmuGetEventCount_(pmuCOUNTER0);
event1_cycles = _pmuGetEventCount_(pmuCOUNTER1);
event2_cycles = _pmuGetEventCount_(pmuCOUNTER2);

If you can show me how the example in Application Report SPNA138A–November 2011 works with the HalCoGen's generated code as i pasted, I will be happy.

0 QJ Wang over 4 years ago in reply to v01d

TI__Guru**** 196776 points

Hi V01d,

I developed an example of using pmu and added to our repo:

http://software-dl.ti.com/hercules/hercules_docs/latest/hercules/Examples/Examples.html#using-performance-monitoring-unit-pmu-to-evaluate-code-efficiency

+1 v01d over 4 years ago in reply to QJ Wang

Expert 2025 points

QJ Wang

No, you still don't see it I think.

The API of sys_pmu.h #defines pmuCOUNTER0/1/2 is non-0 based index , starting at 1.

The _pmuGetEventCount_ asm code then selects & reads out the counter. Note, from ARM's tech ref:

https://developer.arm.com/documentation/ddi0363/e/events-and-performance-monitor/performance-monitoring-registers/c9--performance-counter-selection-register

I thus believe the original code I seen in TI's app note (referred to above in my posts in the thread) is correct, and the LSR instruction is required, I do not understand why HalCoGen removed it.

And, I think your example code thus, has undefined behaviour.

So correct me if I'm wrong then.

0 QJ Wang over 4 years ago in reply to v01d

TI__Guru**** 196776 points

You are correct. Thanks V01d.

I thought pmuCOUNTER0=0, but the pmuCOUNTER0 is defined as 0x1 in HalCoGen generated header file.

0 v01d over 4 years ago in reply to QJ Wang

Expert 2025 points

QJ Wang

Nice, so next time, check that ARM spec before hand :)

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HALCOGEN: HalCoGen generates sys_pmu.asm with missing asm instructions for TMS5701227