I measured the cycles it takes from with _c_int00 to my first call to main(), and I get over 16 ms, running core at 100 Mhz. If this is true, then this is problematic to my system, i need hal to come up with max 7 ms.
I start measuring - using cycle counter in PMU - from after line errata_PBIST_4(); ( Ideally i want to start straight from after PLL is configured & locked but that errata method resets/reconfigures PMU and I'm lazy to record cycles before & after it and add up.. )
Look / stepping blocks , most of the time is spent busy waiting for the self-tests to complete, start - wait serially one by one:
* Run PBIST on STC ROM */
pbistRun((uint32)STC_ROM_PBIST_RAM_GROUP,
((uint32)PBIST_TripleReadSlow | (uint32)PBIST_TripleReadFast));
* Wait for PBIST for STC ROM to be completed */
/*SAFETYMCUSW 28 D MR:NA <APPROVED> "Hardware status bit read check" */
while(pbistIsTestCompleted() != TRUE)
{
}/* Wait */
....
...
* Run PBIST on PBIST ROM */
pbistRun((uint32)PBIST_ROM_PBIST_RAM_GROUP,
((uint32)PBIST_TripleReadSlow | (uint32)PBIST_TripleReadFast));
/* Wait for PBIST for PBIST ROM to be completed */
/*SAFETYMCUSW 28 D MR:NA <APPROVED> "Hardware status bit read check" */
while(pbistIsTestCompleted() != TRUE)
{
}/* Wait */
.....
/* Run PBIST on CPU RAM.
* The PBIST controller needs to be configured separately for single-port and dual-port SRAMs.
* The CPU RAM is a single-port memory. The actual "RAM Group" for all on-chip SRAMs is defined in the
* device datasheet.
*/
pbistRun(0x00300020U, /* ESRAM Single Port PBIST */
(uint32)PBIST_March13N_SP);
/* USER CODE BEGIN (32) */
/* USER CODE END */
/* Wait for PBIST for CPU RAM to be completed */
/*SAFETYMCUSW 28 D MR:NA <APPROVED> "Hardware status bit read check" */
while(pbistIsTestCompleted() != TRUE)
{
}/* Wait */
...
// ( OTHER .. )
Is it not possible to start as many as is ok (by dependency ..?) at once, and wait in the end? Or is the provided code is many as possible tests started at the same time..
What if anything can be sped up here?
