TMS570LS3137: Flexray FTU example project

/*
 * ftu_node1.c
 *
 *  Created on: Oct 6, 2015
 *      Author: a0324020
 */


#include "fray.h"
#include "ftu.h"
#include "LED_Show.h"
#include "file_io.h"
#include "stdio.h"
#include "fray_node_config.h"
#include "sys_vim.h"

#ifdef PMU_CYCLE
#include "sys_pmu.h"
#endif

#if ((FrayNodeNumber == 0) && (FRAY_ENABLE_FTU == 1))

unsigned int g_ftuErrorFlag, g_ftuDataRCVED, g_ftuDataTXED;
unsigned int g_frayErrorFlag, g_frayDataRCVED, g_frayDataTXED;

#ifdef PMU_CYCLE
volatile unsigned long cycles_PMU_start, cycles_PMU_end, cycles_PMU_measure, cycles_PMU_comp, cycles_PMU_code;
volatile float time_PMU_code;
unsigned int seconds_PMU;
#endif //PMU_CYCLE

#define MAX_MSG_LENGTH    16     //maximum TX/RX payload length + header length (4 words)
#define MAX_TXRX_BUFFER    8     //8 buffers are used
#define TX_PLC            16     //2-bytes; payload length: TX_PLC*2=32 bytes, eight 32-bit words

// buffer0, 3, 5 for lot 1, 5, 9; Payload is 16 (32 bytes)
// Check the received data at:
// Buffer0 at 0x00 (offset)
// Buffer1 at offset + MAX_MSG_LENGTH  * 4
// Buffer2 at offset + 2*MAX_MSG_LENGTH  * 4
// Buffer3 at offset + 3*MAX_MSG_LENGTH  * 4; ...
unsigned int FRAY_TX_Payload[36] = {0x27000001, 0x001000F2, 0x00000080, 0x0036C000, //buffer0 header
		                            0x01010101, 0x01010101, 0x01010101,	0x01010101, //buff0 payload
						        	0x55AAFF00,	0x00FFAA55,	0x00000000,	0xdeadbeef, //buff0 payload
									0x27000005, 0x00100005, 0x000000A0, 0x00360000, //buffer1 header
	                                0x05050505, 0x05050505, 0x05050505,	0x05050505, //buff1 payload
								    0x55AAFF00,	0x00FFAA55,	0x00000000,	0xdeadbeef, //buff1 payload
									0x25000009, 0x001003FC, 0x00000200, 0x00360400, //buffer2 header
									0x09090909, 0x09090909, 0x09090909,	0x09090909, //buff1 payload
								    0x55AAFF00,	0x00FFAA55,	0x00000000,	0xdeadbeef  //buff1 payload
							       };

unsigned int FRAY_SysMemory[MAX_TXRX_BUFFER * MAX_MSG_LENGTH];

#pragma DATA_ALIGN (FRAY_SysMemory, 64)

static void configure_node_header(FRAY_ST *Fray_Ptr);
static void triger_tx_static_data(FTU_ST *FTU_Ptr);
static void triger_tx_dynamic_data(FTU_ST *FTU_Ptr);
static void triger_receive_data(FRAY_ST *Fray_Ptr, FTU_ST *FTU_Ptr);

void FTU_Test(FRAY_ST *Fray_Ptr, FTU_ST *FTU_Ptr);

void FTU_Test(FRAY_ST *Fray_Ptr, FTU_ST *FTU_Ptr)
{
	register unsigned int i;

	for (i=0; i<(MAX_TXRX_BUFFER * MAX_MSG_LENGTH); i++)
	   FRAY_SysMemory[i] = 0;

    // buffer 0 is used for TX
	for (i=0; i<(TX_PLC/2+4); i++)
	{
	   FRAY_SysMemory[i] = FRAY_TX_Payload[i];
	}
    // buffer 3 is used for TX, +4 is for header
	for (i=0; i<(TX_PLC/2+4); i++)
	{
	   FRAY_SysMemory[3*MAX_MSG_LENGTH+i] = FRAY_TX_Payload[1*(TX_PLC/2 + 4)+i];
	}
    // buffer 5 is used for TX
	for (i=0; i<(TX_PLC/2 + 4); i++)
	{
	   FRAY_SysMemory[5*MAX_MSG_LENGTH+i] = FRAY_TX_Payload[2*(TX_PLC/2 + 4)+i];
	}

	//Configure the Flexray control registers, enable the interrupts
	Fray_testInit(Fray_Ptr);

	//define the buffer headers and write to FRAY Message RAM
	configure_node_header(Fray_Ptr);

	//Enable FTU, enable the Interrupts, and clear FTU TCR
	FTU_Init(FTU_Ptr, Fray_Ptr, ftuTCR);

	// configure TBA
	FTU_Ptr->TBA_UL = (unsigned int)&FRAY_SysMemory[0];

	// TU RAM Configuration
	// configure Buffer 0/3/5: System-Memory to Communication Controller
	// TX, Manual Transfer
	// set STXRH, transfer Payload only from SRAM to CC
	// Keep in mind that the offset is 32-bit aligned buffer address
	ftuTCR->FTUTCR_ST[0].TCR_UN.TCR_UL = 0x00044000;
	ftuTCR->FTUTCR_ST[3].TCR_UN.TCR_UL = 0x00044000 + MAX_MSG_LENGTH*3;
	ftuTCR->FTUTCR_ST[5].TCR_UN.TCR_UL = 0x00044000 + MAX_MSG_LENGTH*5;

    // configure Buffer 1/6/7: Communication Controller to System-Memory
	// RX, Event Mode, payload only
	// Keep in mind that the offset is 32-bit aligned buffer address
	// Transfer Header and Payload from CC and SRAM
	ftuTCR->FTUTCR_ST[1].TCR_UN.TCR_UL = 0x00030000 + MAX_MSG_LENGTH*1;
	ftuTCR->FTUTCR_ST[6].TCR_UN.TCR_UL = 0x00030000 + MAX_MSG_LENGTH*6;
	ftuTCR->FTUTCR_ST[7].TCR_UN.TCR_UL = 0x00030000 + MAX_MSG_LENGTH*7;

	// Config Event Mode
	// enable Message Buffer 1/6/7 event for transfer to system memory
	if (TransferOnEventToSRAM == 1)
		FTU_Ptr->ETESMS1_UL = 0x00000000 | (0x1 << 1) | (0x1 << 6) | (0x1 << 7);

    FTU_Ptr->GCR_UN.GCR_UL = 0x00000002; // RUN TU

    // Change CC state from CONFIG state to READY state, Also define TXSY and TXST
    // A coldstart node has bits SUCC1.TXST and SUCC1.TXSY set to 1
	Fray_CC_READY(Fray_Ptr, 1, 1);

	// Enable Cold Start
	Fray_AllowColdStart(Fray_Ptr);

	// Change the CC state to RUN
	Fray_StartCommunication(Fray_Ptr);

	// -- Measurement Initialization; want to measure how many cycles are used to receive data from nodes
	#ifdef PMU_CYCLE
	   	    _pmuInit_();
	   	    _pmuEnableCountersGlobal_();
	   	    _pmuSetCountEvent_(pmuCOUNTER0, PMU_CYCLE_COUNT); // PMU_INST_ARCH_EXECUTED
	#endif //PMU_Cycle

	while(1){
	}
}

// Configure the headers for all the msg buffers used on this node
// You can put the headers to FRAY_TX_Payload[] and Transfer to MSG along with the payload
static void configure_node_header(FRAY_ST *Fray_Ptr)
{
	HEADER_ST Header;
	BC_ST BufCMD;
	HEADER_ST *Header_Ptr = &Header;
	BC_ST *BC_Ptr = &BufCMD;

	// Buffer config initialization
	Header_Ptr->mbi  = 1;   // message buffer interrupt
	Header_Ptr->txm  = 0;   // transmission mode - continuous mode
	Header_Ptr->ppit = 0;   // Payload Preamble Indicator
	Header_Ptr->cfg  = 0;   // message buffer configuration bit (0=RX, 1 = TX)
	Header_Ptr->chb  = 1;   // Ch B
	Header_Ptr->cha  = 1;   // Ch A
	Header_Ptr->cyc  = 0;   // Cycle Filtering Code (no cycle filtering)
	Header_Ptr->fid  = 0;   // Frame ID
	Header_Ptr->plc  = 0;   // Payload Length
	Header_Ptr->dp   = 0;   // Pointer to start of data in message RAM
	Header_Ptr->sfi  = 0;   // startup frame indicator
	Header_Ptr->syn  = 0;   // sync frame indicator

	BC_Ptr->ibrh = 0;  // input buffer number
	BC_Ptr->stxrh= 0;  // set transmission request
	BC_Ptr->ldsh = 0;  // load data section
	BC_Ptr->lhsh = 0;  // load header section
	BC_Ptr->ibsyh = 1; // check for input buffer busy shadow
	BC_Ptr->ibsys = 1; // check for input buffer busy host
	BC_Ptr->obrs = 0;  // output buffer number
	BC_Ptr->rdss = 0;  // read data section
	BC_Ptr->rhss = 0;  // read header section

	// Message buffers
    // Message buffer 0 or 1 is dedicated to hold the startup frame, the sync frame, or the designated single slot
    // frame as configured by SUCC1.TXST, SUCC1.TXSY, and SUCC1.TSM in the SUC Configuration register
    // 1. In this case it can be reconfigured in DEFAULT_CONFIG or CONFIG state only. This ensures that any
    // node transmits at most one startup / sync frame per communication cycle.

	// Buffer #0
	// The protocol requires that both bits SUCC1.TXST and SUCC1.TXSY are set
	// for coldstart nodes
	Header_Ptr->fid  = 1;    // frame ID
	Header_Ptr->dp   = 0x80; // Pointer to start of data in message RAM
	Header_Ptr->cfg  = 1;    // TX frame
	Header_Ptr->cyc  = 0x00; //All cycles
	Header_Ptr->syn  = 1;    // sync frame indicator
	Header_Ptr->sfi  = 1;    // startup frame indicator
	Header_Ptr->cha  = 1;    // Ch A
	Header_Ptr->chb  = 1;    // Ch B
	Header_Ptr->plc  = 16;	 // 32 byte payload
	Header_Ptr->crc  = header_crc_calc(Header_Ptr);

	BC_Ptr->lhsh = 1;  // load header section
	BC_Ptr->ibrh = 0;  // input buffer number:0x80, 0x85, 0x8A, 0x8F, 0x94, 0x99, 0x9E, 0xA3

	Fray_PrepareHeader(Fray_Ptr, Header_Ptr);
	Fray_Transmit(Fray_Ptr, BC_Ptr);          //transfer header and data to FRAY MSG RAM

	// Buffer #1, receive msg
	Header_Ptr->fid  = 2;    // frame ID
	Header_Ptr->dp   = 0x88; // Pointer to start of data in message RAM
	Header_Ptr->cfg  = 0;    // RX frame
	Header_Ptr->cyc  = 0x0;  // 0x04; every 4th. 0,4,8,...
	Header_Ptr->syn  = 1;    // sync frame indicator
	Header_Ptr->sfi  = 0;    // startup frame indicator
	Header_Ptr->cha  = 1;    // Ch A
	Header_Ptr->chb  = 1;    // Ch B
	Header_Ptr->plc  =16;
	Header_Ptr->crc  = 0;

	BC_Ptr->lhsh = 1;  // load header section
	BC_Ptr->ibrh = 1;  // input buffer numberinput buffer number:0x80, 0x85, 0x8A, 0x8F, 0x94, 0x99, 0x9E, 0xA3

	Fray_PrepareHeader(Fray_Ptr, Header_Ptr);
	Fray_Transmit(Fray_Ptr, BC_Ptr);          //transfer header and data to FRAY MSG RAM

	// Buffer #3, TX msg
	Header_Ptr->fid  = 5;    // frame ID
	Header_Ptr->dp   = 0xA0; // Pointer to start of data in message RAM
	Header_Ptr->cfg  = 1;    // TX frame
	Header_Ptr->cyc  = 0x0;  //23;  //every 32th cycle at 3/35 cycle
	Header_Ptr->syn  = 0;    // sync frame indicator
	Header_Ptr->sfi  = 0;    // startup frame indicator
	Header_Ptr->cha  = 1;    // Ch A
	Header_Ptr->chb  = 1;    // Ch B
	Header_Ptr->plc  = 16;	 // 32 byte payload
	Header_Ptr->crc  = header_crc_calc(Header_Ptr);

	BC_Ptr->lhsh = 1;  // load header section
	BC_Ptr->ibrh = 3;  // input buffer number:0x80, 0x85, 0x8A, 0x8F, 0x94, 0x99, 0x9E, 0xA3

	Fray_PrepareHeader(Fray_Ptr, Header_Ptr);
	Fray_Transmit(Fray_Ptr, BC_Ptr);          //transfer header and data to FRAY MSG RAM

	// buffer #5   -- dynamic
	Header_Ptr->fid  = 9;   // frame ID
	Header_Ptr->dp   = 0x200; // Pointer to start of data in message RAM
	Header_Ptr->cfg  = 1;    // TX frame
	Header_Ptr->cyc  = 0x26;  //0x26;  //every 32th cycle at 6/38 cycle
	Header_Ptr->syn  = 0;    // sync frame indicator
	Header_Ptr->sfi  = 0;    // startup frame indicator
	Header_Ptr->cha  = 1;    // Ch A
	Header_Ptr->chb  = 0;    // Ch B
	Header_Ptr->plc  = 16;	 // 32 byte payload
	Header_Ptr->crc  = header_crc_calc(Header_Ptr);

	BC_Ptr->lhsh = 1;  // load header section
	BC_Ptr->ibrh = 5;  // input buffer number

	Fray_PrepareHeader(Fray_Ptr, Header_Ptr);
	Fray_Transmit(Fray_Ptr, BC_Ptr);          //transfer header and data to FRAY MSG RAM

	// buffer #6
	Header_Ptr->fid  = 15;     // frame ID
	Header_Ptr->dp   = 0x380; // Pointer to start of data in message RAM
	Header_Ptr->cfg  = 0;    // RX frame
	Header_Ptr->cyc  = 0x0;  //every 14th cycle at 4/20/36/52 cycle
	Header_Ptr->syn  = 0;    // sync frame indicator
	Header_Ptr->sfi  = 0;    // startup frame indicator
	Header_Ptr->cha  = 1;    // Ch A
	Header_Ptr->chb  = 0;    // Ch B
	Header_Ptr->plc  = 16;	 // 32 byte payload
	Header_Ptr->crc  = 0;

	BC_Ptr->lhsh = 1;  // load header section
	BC_Ptr->ibrh = 6;  // input buffer number

	Fray_PrepareHeader(Fray_Ptr, Header_Ptr);
	Fray_Transmit(Fray_Ptr, BC_Ptr);          //transfer header and data to FRAY MSG RAM

	// buffer #7, RX MSG
	Header_Ptr->fid  = 16;     // frame ID
	Header_Ptr->dp   = 0x3C0; // Pointer to start of data in message RAM
	Header_Ptr->cfg  = 0;    // RX frame
	Header_Ptr->cyc  = 0x0;  //every 16th cycle at 3/19/35/51 cycle
	Header_Ptr->syn  = 0;    // sync frame indicator
	Header_Ptr->sfi  = 0;    // startup frame indicator
	Header_Ptr->cha  = 1;    // Ch A
	Header_Ptr->chb  = 0;    // Ch B
	Header_Ptr->plc  = 16;
	Header_Ptr->crc  = 0;

	BC_Ptr->lhsh = 1;  // load header section
	BC_Ptr->ibrh = 7;  // input buffer number

	Fray_PrepareHeader(Fray_Ptr, Header_Ptr);
	Fray_Transmit(Fray_Ptr, BC_Ptr);          //transfer header and data to FRAY MSG RAM
}

// We TX data to MSG RAM at every cycle start. CC will transmit the data to FRAY BUS based on
// the filters defined in the header of the buffer
static void triger_tx_static_data(FTU_ST *FTU_Ptr)
{
	// transfer Message Buffer 0/3 to CC
	FTU_Ptr->TTCCS1_UL  = (0x1 << 0);
	FTU_Ptr->TTCCS1_UL  = (0x1 << 3);
}

// We TX data to MSG RAM at every cycle start. CC will transmit the data to FRAY BUS based on
// the filters defined in the header of the buffer
static void triger_tx_dynamic_data(FTU_ST *FTU_Ptr)
{
	// FTU RAM Configuration
	// configure Buffer 5, LOT 9: System-Memory to Communication Controller
	// TX, Manual Transfer to MSG RAM
	// set STXRH, transfer Payload only
	FTU_Ptr->TTCCS1_UL  = 0x00000000 | 0x01 << 5;    // transfer Message Buffer 5   to CC
}

// This function is used only when the Transfer on EVENT is disabled
// If ETESMS is enabled, the NDAT1 will be zero
static void triger_receive_data(FRAY_ST *Fray_Ptr, FTU_ST *FTU_Ptr)
{
	unsigned int ndat1;

	// IF FTU EVENt is enabled, ndat1 is always 0
	// Buffer is automatically transfered to system memory
	ndat1 = Fray_Ptr->NDAT1_UN.NDAT1_UL;

    if ( 0x2 == (ndat1 & 0x2)) //buffer 1 from Node 1, slot  2
    {
    	FTU_Ptr->TTSMS1_UL   = 0x02;
    }
    if ( 0x40 == (ndat1 & 0x40)) //buffer 6 from Node 1, slot  15
    {
    	FTU_Ptr->TTSMS1_UL   = 0x40;
    }
    if ( 0x80 == (ndat1 & 0x80)) //buffer 7 from Node 1, slot  16
    {
    	FTU_Ptr->TTSMS1_UL  = 0x80;
    }
}

#pragma WEAK(ftuErrorNotification)
void ftuErrorNotification(FTU_ST *FTU_Ptr, unsigned int notification)
{
   register int eFlag;

   eFlag = FTU_Ptr->TEIR_UN.TEIR_UL;

   if(0x01 == (eFlag & 0x01)){
	   //FAC error
    	g_ftuErrorFlag = 1;
   	    gio_LED_Blinky(3);
   }
   if(0x02 == (eFlag & 0x02)){
	   //TNR error
	   g_ftuErrorFlag = 1;
  	   gio_LED_Blinky(3);
   }
   if(0x0 != (eFlag & 0x070)){
	   //WSTAT error
	   g_ftuErrorFlag = 1;
  	   gio_LED_Blinky(3);
   }
   if(0x0 != (eFlag & 0x700)){
	   //RSTAT error
	   g_ftuErrorFlag = 1;
  	   gio_LED_Blinky(3);
   }
   if(0x10000 == (eFlag & 0x10000)){
	   //Parity error
	   g_ftuErrorFlag = 1;
  	   gio_LED_Blinky(3);
   }
   if(0x20000 == (eFlag & 0x20000)){
	   //MPV error
	   g_ftuErrorFlag = 1;
  	   gio_LED_Blinky(3);
   }

}


#pragma WEAK(ftuStatusChangeNotification)
void ftuStatusChangeNotification(FTU_ST *FTU_Ptr, unsigned int notification)
{
#define BUF1_RX    0x002
#define BUF6_RX    0x007
#define BUF7_RX    0x008

#define BUF0_TX    0x101
#define BUF3_TX    0x104
#define BUF5_TX    0x106

	register int vect;

	vect= notification;
	gio_LED_Blinky(2);

    if( 0 != (vect & (BUF1_RX | BUF6_RX | BUF7_RX)))
    {
    	g_ftuDataRCVED = 1;       //RX
		if (frayREG1->MTCCV_UN.MTCCV_ST.ccv_B6 == 0x20)
 			  gio_LED_Blinky(7);
	}
}

#pragma WEAK(frayErrorNotification)
void frayErrorNotification(FRAY_ST *Fray_PST, unsigned int notification)
{
	 gio_LED_Blinky(3);
}

#pragma WEAK(frayStatusChangeNotification)
void frayStatusChangeNotification(FRAY_ST *Fray_Ptr, unsigned int notification)
{
   	// -- Measurement Execution --
#ifdef PMU_CYCLE
   		_pmuResetCounters_();
   		_pmuStartCounters_(pmuCOUNTER0);
   		cycles_PMU_start = _pmuGetEventCount_(pmuCOUNTER0);
#endif //PMU_Cycle
	gio_LED_Blinky(1);

   	if (notification == ( 0x1 << 2))   //CYCS
	{
		triger_tx_static_data(ftuREG);
		if (Fray_Ptr->MTCCV_UN.MTCCV_ST.ccv_B6 == 0x10)
 			  gio_LED_Blinky(0);

	}
	//Only when RXI Fray INT is defined, and the Transfer On Event is disabled
	if ((notification == (1 << 4)) && (TransferOnEventToSRAM == 0))   //RXI
        triger_receive_data(Fray_Ptr, ftuREG);   //used if transfer on FTU EVEN is disabled

	if (notification == ( 0x1 << 15))   //SDS
	{
		triger_tx_dynamic_data(ftuREG);
		if (Fray_Ptr->MTCCV_UN.MTCCV_ST.ccv_B6 == 0x10)
 			  gio_LED_Blinky(1);

	}
#ifdef PMU_CYCLE
	_pmuStopCounters_(pmuCOUNTER0);
	cycles_PMU_end = _pmuGetEventCount_(pmuCOUNTER0);
	cycles_PMU_measure = cycles_PMU_end - cycles_PMU_start;
	seconds_PMU = cycles_PMU_measure / (180000000);
#endif //PMU_Cycle
}

#endif

/*
 * ftu_node1.c
 *
 *  Created on: Oct 6, 2015
 *      Author: a0324020
 */


#include "fray.h"
#include "ftu.h"
#include "LED_Show.h"
#include "file_io.h"
#include "stdio.h"
#include "fray_node_config.h"
#include "sys_vim.h"

#ifdef PMU_CYCLE
#include "sys_pmu.h"
#endif

#if ((FrayNodeNumber == 1) && (FRAY_ENABLE_FTU == 1))

unsigned int g_ftuErrorFlag, g_ftuDataRCVED, g_ftuDataTXED;
unsigned int g_frayErrorFlag, g_frayDataRCVED, g_frayDataTXED;

#define MAX_MSG_LENGTH    16     //maximum TX/RX payload length + header length (4 words)
#define MAX_TXRX_BUFFER    8     //8 buffers are used
#define TX_PLC            16     //2-bytes; payload length: TX_PLC*2=32 bytes, eight 32-bit words

// buffer0, 3, 5 for lot 1, 5, 9; Payload is 16 (32 bytes)
// Check the received data at:
// Buffer0 at 0x00 (offset)
// Buffer1 at offset + MAX_MSG_LENGTH  * 4
// Buffer2 at offset + 2*MAX_MSG_LENGTH  * 4
// Buffer3 at offset + 3*MAX_MSG_LENGTH  * 4; ...
unsigned int FRAY_TX_Payload[36] = {0x00000000, 0x00000000, 0x00000000, 0x00000000, //buffer0 header
		                            0x12121212, 0x12121212, 0x12121212,	0x12121212, //buff0 payload
						        	0x55AAFF00,	0x00FFAA55,	0x00000000,	0xdeadbeef, //buff0 payload
									0x00000000, 0x00000000, 0x00000000, 0x00000000, //buffer1 header
	                                0x1F1F1F1F, 0x1F1F1F1F, 0x1F1F1F1F,	0x1F1F1F1F, //buff1 payload
								    0x55AAFF00,	0x00FFAA55,	0x00000000,	0xdeadbeef, //buff1 payload
									0x00000000, 0x00000000, 0x00000000, 0x00000000, //buffer2 header
									0x10101010, 1010101010, 0x10101010,	0x10101010, //buff1 payload
								    0x55AAFF00,	0x00FFAA55,	0x00000000,	0xdeadbeef  //buff1 payload
							       };

unsigned int FRAY_SysMemory[MAX_TXRX_BUFFER * MAX_MSG_LENGTH];

#pragma DATA_ALIGN (FRAY_SysMemory, 64)

static void configure_node_header(FRAY_ST *Fray_Ptr);
static void triger_tx_static_data(FTU_ST *FTU_Ptr);
static void triger_tx_dynamic_data(FTU_ST *FTU_Ptr);
static void triger_receive_data(FRAY_ST *Fray_Ptr, FTU_ST *FTU_Ptr);

void FTU_Test(FRAY_ST *Fray_Ptr, FTU_ST *FTU_Ptr);

void FTU_Test(FRAY_ST *Fray_Ptr, FTU_ST *FTU_Ptr)
{
	register unsigned int i;

	for (i=0; i<(MAX_TXRX_BUFFER * MAX_MSG_LENGTH); i++)
	   FRAY_SysMemory[i] = 0;

    // buffer 0 is used for TX
	for (i=0; i<(TX_PLC/2+4); i++)
	{
	   FRAY_SysMemory[i] = FRAY_TX_Payload[i];
	}
    // buffer 3 is used for TX, +4 is for header
	for (i=0; i<(TX_PLC/2+4); i++)
	{
	   FRAY_SysMemory[3*MAX_MSG_LENGTH+i] = FRAY_TX_Payload[1*(TX_PLC/2 + 4)+i];
	}
    // buffer 5 is used for TX
	for (i=0; i<(TX_PLC/2 + 4); i++)
	{
	   FRAY_SysMemory[5*MAX_MSG_LENGTH+i] = FRAY_TX_Payload[2*(TX_PLC/2 + 4)+i];
	}

	//Configure the Flexray control registers, enable the interrupts
	Fray_testInit(Fray_Ptr);

	//define the buffer headers and write to FRAY Message RAM
	configure_node_header(Fray_Ptr);

	//Enable FTU, enable the Interrupts, and clear FTU TCR
	FTU_Init(FTU_Ptr, Fray_Ptr, ftuTCR);

	// configure TBA
	FTU_Ptr->TBA_UL = (unsigned int)&FRAY_SysMemory[0];

	// TU RAM Configuration
	// configure Buffer 0/6/7: System-Memory to Communication Controller
	// TX, Manual Transfer
	// set STXRH, transfer Payload only from SRAM to CC
	// Keep in mind that the offset is 32-bit aligned buffer address
	ftuTCR->FTUTCR_ST[0].TCR_UN.TCR_UL = 0x00044000;
	ftuTCR->FTUTCR_ST[6].TCR_UN.TCR_UL = 0x00044000 + MAX_MSG_LENGTH*6;
	ftuTCR->FTUTCR_ST[7].TCR_UN.TCR_UL = 0x00044000 + MAX_MSG_LENGTH*7;

    // configure Buffer 1/2/3/5: Communication Controller to System-Memory
	// RX, Event Mode, payload only
	// Keep in mind that the offset is 32-bit aligned buffer address
	// Transfer Header and Payload from CC and SRAM
	ftuTCR->FTUTCR_ST[1].TCR_UN.TCR_UL = 0x00030000 + MAX_MSG_LENGTH*1;
	ftuTCR->FTUTCR_ST[2].TCR_UN.TCR_UL = 0x00030000 + MAX_MSG_LENGTH*2;
	ftuTCR->FTUTCR_ST[3].TCR_UN.TCR_UL = 0x00030000 + MAX_MSG_LENGTH*3;
	ftuTCR->FTUTCR_ST[5].TCR_UN.TCR_UL = 0x00030000 + MAX_MSG_LENGTH*5;

	// Config Event Mode
	// enable Message Buffer 1/6/7 event for transfer to system memory
	if (TransferOnEventToSRAM == 1)
		FTU_Ptr->ETESMS1_UL = 0x00000000 | (0x1 << 1) | (0x1 << 2) | (0x1 << 3) | (0x1 << 5);

    FTU_Ptr->GCR_UN.GCR_UL = 0x00000002; // RUN TU

    // Change CC state from CONFIG state to READY state, Also define TXSY and TXST
    // A coldstart node has bits SUCC1.TXST and SUCC1.TXSY set to 1
	Fray_CC_READY(Fray_Ptr, 1, 1);

	// Enable Cold Start
	Fray_AllowColdStart(Fray_Ptr);

	// Change the CC state to RUN
	Fray_StartCommunication(Fray_Ptr);

	while(1){
	}
}

// Configure the headers for all the msg buffers used on this node
// You can put the headers to FRAY_TX_Payload[] and Transfer to MSG along with the payload
static void configure_node_header(FRAY_ST *Fray_Ptr)
{
	HEADER_ST Header;
	BC_ST BufCMD;
	HEADER_ST *Header_Ptr = &Header;
	BC_ST *BC_Ptr = &BufCMD;

	// Buffer config initialization
	Header_Ptr->mbi  = 1;   // message buffer interrupt
	Header_Ptr->txm  = 0;   // transmission mode - continuous mode
	Header_Ptr->ppit = 0;   // Payload Preamble Indicator
	Header_Ptr->cfg  = 0;   // message buffer configuration bit (0=RX, 1 = TX)
	Header_Ptr->chb  = 1;   // Ch B
	Header_Ptr->cha  = 1;   // Ch A
	Header_Ptr->cyc  = 0;   // Cycle Filtering Code (no cycle filtering)
	Header_Ptr->fid  = 0;   // Frame ID
	Header_Ptr->plc  = 0;   // Payload Length
	Header_Ptr->dp   = 0;   // Pointer to start of data in message RAM
	Header_Ptr->sfi  = 0;   // startup frame indicator
	Header_Ptr->syn  = 0;   // sync frame indicator

	BC_Ptr->ibrh = 0;  // input buffer number
	BC_Ptr->stxrh= 0;  // set transmission request
	BC_Ptr->ldsh = 0;  // load data section
	BC_Ptr->lhsh = 0;  // load header section
	BC_Ptr->ibsyh = 1; // check for input buffer busy shadow
	BC_Ptr->ibsys = 1; // check for input buffer busy host
	BC_Ptr->obrs = 0;  // output buffer number
	BC_Ptr->rdss = 0;  // read data section
	BC_Ptr->rhss = 0;  // read header section

	// Message buffers
    // Message buffer 0 or 1 is dedicated to hold the startup frame, the sync frame, or the designated single slot
    // frame as configured by SUCC1.TXST, SUCC1.TXSY, and SUCC1.TSM in the SUC Configuration register
    // 1. In this case it can be reconfigured in DEFAULT_CONFIG or CONFIG state only. This ensures that any
    // node transmits at most one startup / sync frame per communication cycle.

// Static Segement MSG
	// Buffer #1, RX MSG
	Header_Ptr->fid  = 1;    // frame ID
	Header_Ptr->dp   = 0x80; // Pointer to start of data in message RAM
	Header_Ptr->cfg  = 0;    // RX frame
	Header_Ptr->cyc  = 0x11;  //every 16th cycle at 1/17/33/49 cycle
	Header_Ptr->syn  = 1;    // sync frame indicator
	Header_Ptr->sfi  = 0;    // startup frame indicator
	Header_Ptr->cha  = 1;    // Ch A
	Header_Ptr->chb  = 1;    // Ch B
	Header_Ptr->plc  = 16;
	Header_Ptr->crc  = 0;

	BC_Ptr->lhsh = 1;  // load header section
	BC_Ptr->ibrh = 1;  // input buffer number:0x80, 0x85, 0x8A, 0x8F, 0x94, 0x99, 0x9E, 0xA3

	Fray_PrepareHeader(Fray_Ptr, Header_Ptr);
	Fray_Transmit(Fray_Ptr, BC_Ptr);          //transfer header and data to FRAY MSG RAM

	// Buffer #0, TX MSG
	Header_Ptr->fid  = 2;    // frame ID
	Header_Ptr->dp   = 0x88; // Pointer to start of data in message RAM
	Header_Ptr->cfg  = 1;    // TX frame
	Header_Ptr->cyc  = 0x00; // all cycles
	Header_Ptr->syn  = 1;    // sync frame indicator
	Header_Ptr->sfi  = 1;    // startup frame indicator
	Header_Ptr->cha  = 1;    // Ch A
	Header_Ptr->chb  = 1;    // Ch B
	Header_Ptr->plc  = 16;   // 32 byte payload
	Header_Ptr->crc  = header_crc_calc(Header_Ptr);

	BC_Ptr->lhsh = 1;  // load header section
	BC_Ptr->ibrh = 0;  // input buffer numberinput buffer number:0x80, 0x85, 0x8A, 0x8F, 0x94, 0x99, 0x9E, 0xA3

	Fray_PrepareHeader(Fray_Ptr, Header_Ptr);
	Fray_Transmit(Fray_Ptr, BC_Ptr);          //transfer header and data to FRAY MSG RAM

	// Buffer #3, receive msg
	Header_Ptr->fid  = 7;    // frame ID
	Header_Ptr->dp   = 0x9E; // Pointer to start of data in message RAM
	Header_Ptr->cfg  = 0;    // RX frame
	Header_Ptr->cyc  = 0x49;  //every 64th cycle at 9
	Header_Ptr->syn  = 0;    // sync frame indicator
	Header_Ptr->sfi  = 0;    // startup frame indicator
	Header_Ptr->cha  = 1;    // Ch A
	Header_Ptr->chb  = 1;    // Ch B
	Header_Ptr->plc  = 16;
	Header_Ptr->crc  = 0;

	BC_Ptr->lhsh = 1;  // load header section
	BC_Ptr->ibrh = 3;  // input buffer number:0x80, 0x85, 0x8A, 0x8F, 0x94, 0x99, 0x9E, 0xA3

	Fray_PrepareHeader(Fray_Ptr, Header_Ptr);
	Fray_Transmit(Fray_Ptr, BC_Ptr);          //transfer header and data to FRAY MSG RAM

	// buffer #2   RX MSG
	Header_Ptr->fid  = 8;   // frame ID
	Header_Ptr->dp   = 0xB8; // Pointer to start of data in message RAM
	Header_Ptr->cfg  = 0;    // RX frame
	Header_Ptr->cyc  = 0x18;  //every 16th cycle at 8/24/40/56 cycle
	Header_Ptr->syn  = 0;    // sync frame indicator
	Header_Ptr->sfi  = 0;    // startup frame indicator
	Header_Ptr->cha  = 1;    // Ch A
	Header_Ptr->chb  = 1;    // Ch B
	Header_Ptr->plc  = 16;	 // 24 byte payload
	Header_Ptr->crc  = 0;

	BC_Ptr->lhsh = 1;  // load header section
	BC_Ptr->ibrh = 2;  // input buffer number

	Fray_PrepareHeader(Fray_Ptr, Header_Ptr);
	Fray_Transmit(Fray_Ptr, BC_Ptr);          //transfer header and data to FRAY MSG RAM

// Dynamic Segement MSG
	// buffer #5, RX NSG
	Header_Ptr->fid  = 9;     // frame ID
	Header_Ptr->dp   = 0x200; // Pointer to start of data in message RAM
	Header_Ptr->cfg  = 0;    // RX frame
	Header_Ptr->cyc  = 0x26;  //every 32th cycle at 6/38 cycle
	Header_Ptr->syn  = 0;    // sync frame indicator
	Header_Ptr->sfi  = 0;    // startup frame indicator
	Header_Ptr->cha  = 1;    // Ch A
	Header_Ptr->chb  = 0;    // Ch B
	Header_Ptr->plc  = 16;
	Header_Ptr->crc  = 0;

	BC_Ptr->lhsh = 1;  // load header section
	BC_Ptr->ibrh = 5;  // input buffer number

	Fray_PrepareHeader(Fray_Ptr, Header_Ptr);
	Fray_Transmit(Fray_Ptr, BC_Ptr);          //transfer header and data to FRAY MSG RAM

	// buffer #6, TX MSG
	Header_Ptr->fid  = 15;     // frame ID
	Header_Ptr->dp   = 0x380; // Pointer to start of data in message RAM
	Header_Ptr->cfg  = 1;    // TX frame
	Header_Ptr->cyc  = 0x04;  //every 4th cycle at 0/4...cycle
	Header_Ptr->syn  = 0;    // sync frame indicator
	Header_Ptr->sfi  = 0;    // startup frame indicator
	Header_Ptr->cha  = 1;    // Ch A
	Header_Ptr->chb  = 0;    // No transmission on Ch B
	Header_Ptr->plc  = 16;	 // 32 byte payload
	Header_Ptr->crc  = header_crc_calc(Header_Ptr);

	BC_Ptr->lhsh = 1;  // load header section
	BC_Ptr->ibrh = 6;  // input buffer number

	Fray_PrepareHeader(Fray_Ptr, Header_Ptr);
	Fray_Transmit(Fray_Ptr, BC_Ptr);          //transfer header and data to FRAY MSG RAM

	// buffer #7, TX MSG
	Header_Ptr->fid  = 16;     // frame ID
	Header_Ptr->dp   = 0x3C0; // Pointer to start of data in message RAM
	Header_Ptr->cfg  = 1;    // TX frame
	Header_Ptr->cyc  = 0x03;  //every 2nd cycle at 1/3/5... cycle
	Header_Ptr->syn  = 0;    // sync frame indicator
	Header_Ptr->sfi  = 0;    // startup frame indicator
	Header_Ptr->cha  = 1;    // Ch A
	Header_Ptr->chb  = 0;    // No transmission on Ch B
	Header_Ptr->plc  = 16;	 // 32 byte payload
	Header_Ptr->crc  = header_crc_calc(Header_Ptr);

	BC_Ptr->lhsh = 1;  // load header section
	BC_Ptr->ibrh = 7;  // input buffer number

	Fray_PrepareHeader(Fray_Ptr, Header_Ptr);
	Fray_Transmit(Fray_Ptr, BC_Ptr);          //transfer header and data to FRAY MSG RAM
}

// We TX data to MSG RAM at every cycle start. CC will transmit the data to FRAY BUS based on
// the filters defined in the header of the buffer
static void triger_tx_static_data(FTU_ST *FTU_Ptr)
{
	// transfer Message Buffer 0 to CC, LOT 2
	FTU_Ptr->TTCCS1_UL  = (0x1 << 0);
}

// We TX data to MSG RAM at every cycle start. CC will transmit the data to FRAY BUS based on
// the filters defined in the header of the buffer
static void triger_tx_dynamic_data(FTU_ST *FTU_Ptr)
{
	// FTU RAM Configuration
	// configure Buffer 6/7, LOT 15/16: System-Memory to Communication Controller
	// TX, Manual Transfer to MSG RAM
	// set STXRH, transfer Payload only
	FTU_Ptr->TTCCS1_UL  = 0x01 << 6;    // transfer Message Buffer 6   to CC
	FTU_Ptr->TTCCS1_UL  = 0x01 << 7;    // transfer Message Buffer 7   to CC
}

// This function is used only when the Transfer on EVENT is disabled
// If ETESMS is enabled, the NDAT1 will be zero
static void triger_receive_data(FRAY_ST *Fray_Ptr, FTU_ST *FTU_Ptr)
{
	unsigned int ndat1;

	// IF FTU EVENt is enabled, ndat1 is always 0
	// Buffer is automatically transfered to system memory
	ndat1 = Fray_Ptr->NDAT1_UN.NDAT1_UL;

    if ( 0x2 == (ndat1 & 0x2)) //buffer 1 from Node 0, slot  1
    {
    	FTU_Ptr->TTSMS1_UL   = 0x02;
    }
    if ( 0x04 == (ndat1 & 0x04)) //buffer 2 from Node 2, slot  8
    {
    	FTU_Ptr->TTSMS1_UL   = 0x04;
    }
    if ( 0x08 == (ndat1 & 0x08)) //buffer 3 from Node 3, slot  7
    {
    	FTU_Ptr->TTSMS1_UL  = 0x08;
    }
    if ( 0x10 == (ndat1 & 0x10)) //buffer 5 from Node 3, slot  9
    {
    	FTU_Ptr->TTSMS1_UL  = 0x10;
    }
}

#pragma WEAK(ftuErrorNotification)
void ftuErrorNotification(FTU_ST *FTU_Ptr, unsigned int notification)
{
   register int eFlag;

   eFlag = FTU_Ptr->TEIR_UN.TEIR_UL;

   if(0x01 == (eFlag & 0x01)){
	   //FAC error
    	g_ftuErrorFlag = 1;
        gio_LED_Blinky(3);
   }
   if(0x02 == (eFlag & 0x02)){
	   //TNR error
	   g_ftuErrorFlag = 1;
       gio_LED_Blinky(3);
   }
   if(0x0 != (eFlag & 0x070)){
	   //WSTAT error
	   g_ftuErrorFlag = 1;
       gio_LED_Blinky(3);
   }
   if(0x0 != (eFlag & 0x700)){
	   //RSTAT error
	   g_ftuErrorFlag = 1;
       gio_LED_Blinky(3);
   }
   if(0x10000 == (eFlag & 0x10000)){
	   //Parity error
	   g_ftuErrorFlag = 1;
       gio_LED_Blinky(3);
   }
   if(0x20000 == (eFlag & 0x20000)){
	   //MPV error
	   g_ftuErrorFlag = 1;
       gio_LED_Blinky(3);
   }

}


#pragma WEAK(ftuStatusChangeNotification)
void ftuStatusChangeNotification(FTU_ST *Fray_Ptr, unsigned int notification)
{
#define BUF1_RX    0x002
#define BUF2_RX    0x003
#define BUF3_RX    0x004
#define BUF5_RX    0x006

#define BUF0_TX    0x101
#define BUF6_TX    0x107
#define BUF7_TX    0x108

	register int vect;

	vect= notification;
    if( 0 != (vect & (BUF1_RX | BUF2_RX | BUF3_RX | BUF5_RX)))
    {
    	g_ftuDataRCVED = 1;       //RX
		if (frayREG1->MTCCV_UN.MTCCV_ST.ccv_B6 == 0x20)
 			  gio_LED_Blinky(7);
	}
}

#pragma WEAK(frayErrorNotification)
void frayErrorNotification(FRAY_ST *Fray_PST, unsigned int notification)
{
	 gio_LED_Blinky(3);
}

#pragma WEAK(frayStatusChangeNotification)
void frayStatusChangeNotification(FRAY_ST *Fray_Ptr, unsigned int notification)
{
	if (notification == ( 0x1 << 2))   //CYCS
	{
		triger_tx_static_data(ftuREG);
		if (Fray_Ptr->MTCCV_UN.MTCCV_ST.ccv_B6 == 0x10)
 			  gio_LED_Blinky(0);
	}
	//Only when RXI Fray INT is defined, and the Transfer On Event is disabled
	if ((notification == (1 << 4)) && (TransferOnEventToSRAM == 0))   //RXI
        triger_receive_data(Fray_Ptr, ftuREG);   //used if transfer on FTU EVEN is disabled

	if (notification == ( 0x1 << 15))   //SDS
	{
		triger_tx_dynamic_data(ftuREG);
		if (Fray_Ptr->MTCCV_UN.MTCCV_ST.ccv_B6 == 0x10)
 			  gio_LED_Blinky(1);

	}
}

#endif

/*
 * ftu.c
 *
 *  Created on: Sep 22, 2015
 *      Author: a0324020
 */

#include "ftu.h"
#include "fray.h"
#include "fray_node_config.h"
#include "sys_vim.h"

#if (FRAY_ENABLE_FTU == 1)

void FTU_Init(FTU_ST *FTU_Ptr, FRAY_ST *FRAY_Ptr, FTURAM_ST *TCR_Ptr)
{
    unsigned int i;
	//Clear CCTC, TTSM, ETESM. Disable Parity protection
    //Enable FTU
	FTU_Ptr->GCS_UN.GCS_UL = 0x00057033;

	//config the TBA and TCR
	FTU_Ptr->SAMP_UL = 0x08000000;
	FTU_Ptr->EAMP_UL = 0x08040000;

	for (i=0; i< 128; i++)
		TCR_Ptr->FTUTCR_ST[i].TCR_UN.TCR_UL = 0x00000000;

	//enable FTU transfer status interrupt line
	FTU_Ptr->GCS_UN.GCS_ST.SILE_B1 = 0x1;

	//enable FTU error interrupt line
	FTU_Ptr->GCS_UN.GCS_ST.EILE_B1 = 0x1;

	//enable all the transfer error interrupts
	FTU_Ptr->TEIRES_UN.TEIRES_UL = 0x773;

	//enable the interrupt in the FTU.
	// buffers (to CC) interrupt enabled, we only use 8 buffers
	FTU_Ptr->TCCIES1_UL = 0x0000FFFF;

	//buffers (to system memory) interrupt enabled
    FTU_Ptr->TSMIES1_UL = 0x0000FFFF;

	//Enable FTU
	FTU_Ptr->GCS_UN.GCS_UL |= 0x1;  //Enable FTU

    // RUN FTU
	//FTU_Ptr->GCR_UN.GCR_UL = 0x00000002; // RUN TU
}


/*--------------------------------------------------------------------------*/
/* TCR transfer initialization */
/* int TCR_Init(int channel, int header, int payload, int offset, int dir) */
/* */
/* int channel:FTU channel */
/* int header:  1: transfers header;    0: no header transfer */
/* int payload: 1: transfers payload;   0: no payload transfer */
/* int dir:     1: transfer to SM;      0: transfer to CC */
/* int offset: transfer start offset */
/* */
/* returns 0 */
/*--------------------------------------------------------------------------*/
int FTU_TCR_Init(FTURAM_ST *TCR_Ptr, int channel, int header, int payload, int offset, int dir)
{
	int value = 0;
	if (dir != 0) // if direction is other than to CC
	dir = 2; // direction will be SM
	value = value + (header << (15 + dir));
	value = value + (payload << (14 + dir));
	value = value + offset;
	TCR_Ptr->FTUTCR_ST[channel].TCR_UN.TCR_UL = value;
	return(0);
}

void FTU_Enable(FTU_ST *FTU_Ptr)
{
	FTU_Ptr->GCS_UN.GCS_UL |= 0x01;// enable FTU
}

void FTU_Disable(FTU_ST *FTU_Ptr)
{
	FTU_Ptr->GCR_UN.GCR_UL |= 0x01;// disable FTU
}

// Transfer to SM interrupt enable/Disable
// TSMIES registers
int FTU_TOSM_IntEnable(FTU_ST *FTU_Ptr, int TSMIE0_val, int TSMIE1_val, int TSMIE2_val, int TSMIE3_val)
{
	// transfer to SM
	FTU_Ptr->TSMIES1_UL = TSMIE0_val;
	FTU_Ptr->TSMIES2_UL = TSMIE1_val;
	FTU_Ptr->TSMIES3_UL = TSMIE2_val;
	FTU_Ptr->TSMIES4_UL = TSMIE3_val;
	return 0;
}

// Transfer to CC interrupt enable/Disable
// TCCIES registers
int FTU_TOCC_IntEnable(FTU_ST *FTU_Ptr, int TCCIE0_val, int TCCIE1_val, int TCCIE2_val, int TCCIE3_val)
{
	// transfer to CC
	FTU_Ptr->TCCIES1_UL = TCCIE0_val;
	FTU_Ptr->TCCIES2_UL = TCCIE1_val;
	FTU_Ptr->TCCIES3_UL = TCCIE2_val;
	FTU_Ptr->TCCIES4_UL = TCCIE3_val;
	return 0;
}

// Trigger the Transfer to System Memory
// TTSMS registers
int FTU_TOSM_Trigger(FTU_ST *FTU_Ptr, int TTSM0_val, int TTSM1_val, int TTSM2_val, int TTSM3_val)
{
	// transfer to buffer
	FTU_Ptr->TTSMS1_UL = TTSM0_val;
	FTU_Ptr->TTSMS2_UL = TTSM1_val;
	FTU_Ptr->TTSMS3_UL = TTSM2_val;
	FTU_Ptr->TTSMS4_UL = TTSM3_val;
	return 0;
}

// Trigger the Transfer to Communication Controller
// TTCCS registers
int FTU_TOCC_Trigger(FTU_ST *FTU_Ptr, int TTCC0_val, int TTCC1_val, int TTCC2_val, int TTCC3_val)
{
	// transfer to buffer
	FTU_Ptr->TTCCS1_UL = TTCC0_val;
	FTU_Ptr->TTCCS2_UL = TTCC1_val;
	FTU_Ptr->TTCCS3_UL = TTCC2_val;
	FTU_Ptr->TTCCS4_UL = TTCC3_val;
	return 0;
}

//Enable/Disable Transfer on Event to System Memory
int FTU_Event_ETESMS(FTU_ST *FTU_Ptr, int ETESM0_val, int ETESM1_val, int ETESM2_val, int ETESM3_val)
{
	// transfer to SM
	FTU_Ptr->ETESMS1_UL = ETESM0_val;
	FTU_Ptr->ETESMS2_UL = ETESM1_val;
	FTU_Ptr->ETESMS3_UL = ETESM2_val;
	FTU_Ptr->ETESMS4_UL = ETESM3_val;
	return 0;
}

void FTU_Transfer_INT_Enable(FTU_ST *FTU_Ptr)
{
	FTU_Ptr->GCS_UN.GCS_UL |= (0x01 << 5);   // enable int0
}

void FTU_Error_INT_Enable(FTU_ST *FTU_Ptr)
{
	FTU_Ptr->GCS_UN.GCS_UL |= (0x01 << 4);   // enable int1
}

/*--------------------------------------------------------------*/
/* Clear Event to System Memory register*/
/* void FTU_ETESM_clear() */
/*--------------------------------------------------------------*/
void FTU_ETESM_Clear(FTU_ST *FTU_Ptr)
{
	FTU_Ptr->GCS_UN.GCS_UL = 1<<14;
	FTU_Ptr->GCR_UN.GCR_UL = 1<<14;
}
/*---------------------------------------------------------------*/
/* Clear Trigger Transfer to Communication Controller register */
/* void FTU_TTCC_clear() */
/*---------------------------------------------------------------*/
void FTU_TTCC_Clear(FTU_ST *FTU_Ptr)
{
	FTU_Ptr->GCS_UN.GCS_UL = 1<<13;
	FTU_Ptr->GCR_UN.GCR_UL = 1<<13;
}
/*---------------------------------------------------------------*/
/* Clear Trigger Transfer to System Memory register */
/* void FTU_TTSM_clear() */
/*---------------------------------------------------------------*/
void FTU_TTSM_Clear(FTU_ST *FTU_Ptr)
{
	FTU_Ptr->GCS_UN.GCS_UL = 1<<12;
	FTU_Ptr->GCR_UN.GCR_UL = 1<<12;
}


/** @fn void frayLowLevelInterrupt(void)
*   @brief FRAY Level 1 Interrupt Handler
*/
#pragma CODE_STATE(ftuTransferInterrupt, 32)
#pragma INTERRUPT(ftuTransferInterrupt, IRQ)

void ftuTransferInterrupt(void)
{
	unsigned int i, j, k;
	j = ftuREG->TCCO1_UL;
	k = ftuREG->TSMO1_UL;
	i = ftuREG->TOFF_UN.TOFF_UL;
	ftuStatusChangeNotification(ftuREG, i);
}

/** @fn void frayLowLevelInterrupt(void)
*   @brief FRAY Level 1 Interrupt Handler
*/
#pragma CODE_STATE(ftuErrorInterrupt, 32)
#pragma INTERRUPT(ftuErrorInterrupt, IRQ)
void ftuErrorInterrupt(void)
{
	ftuErrorNotification(ftuREG, 0);
}

#else

#pragma CODE_STATE(ftuTransferInterrupt, 32)
#pragma INTERRUPT(ftuTransferInterrupt, IR)

void ftuTransferInterrupt(void)
{
}

/** @fn void frayLowLevelInterrupt(void)
*   @brief FRAY Level 1 Interrupt Handler
*/
#pragma CODE_STATE(ftuErrorInterrupt, 32)
#pragma INTERRUPT(ftuErrorInterrupt, IRQ)
void ftuErrorInterrupt(void)
{
}
#endif