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TMS570LC4357: ECC 1-bit and 2-bit error injecting failed

Part Number: TMS570LC4357
Other Parts Discussed in Thread: HALCOGEN

Hello Team,

I'm writing code to test the functionality of RAM ECC by injecting 1-bit  and 2-bit errors. Also attempting to trigger the ESM low interrupt when an SRAM single bit error occurs.

Kindly let me know if the below mentioned steps are correct or is there any thing missing  .These are the steps I have followed ->

  1. Enable ECC detection, Enable single-bit error status capture, and ESM notification and ECC memory writes are enabled using RAMCTRL

        RAMCTRL = ((0xA << 0) | (0x1<<4) | (0x1 << 8));

  2. Write to memory -> (*(volatile uint32 *)(0x08000000 )) = 0x8421842184218421;

  3. Insert 1 bit ECC error by flip one bit
    uint32 ecc1 = *(volatile uint32 *)(0x08400000U) ^ 0x01 ;

  4. Read the corrupted data to generate single bit error 
    eccram_read1 = (*(volatile uint32 *)(0x08000000 ));

  5.  Check the ESM flag  Q: is theer any extra steps to be handled to check the esm error ?

/* Include Files */

#include "HL_sys_common.h"

/* USER CODE BEGIN (1) */
#include "HL_reg_l2ramw.h"
#include <stdio.h>
/* USER CODE END */

/** @fn void main(void)
 *   @brief Application main function
 *   @note This function is empty by default.
 *
 *   This function is called after startup.
 *   The user can use this function to implement the application.
 */

/* USER CODE BEGIN (2) */

void checkSinglebitECC(void);
void checkDoublebitECC(void);

/* USER CODE END */

int main(void)
{
    /* USER CODE BEGIN (3) */

    checkSinglebitECC();             /* function called to inject and check single bit error mechanism*/
    checkDoublebitECC();             /* function called to inject and check Double bit error mechanism*/

    /* USER CODE END */

    return 0;
}


/* USER CODE BEGIN (4) */

void checkSinglebitECC(void)
{
    volatile uint64 eccram_read1 = 0U;                     /* variable to hold the corrupted data to generate single bit error */

    /* Enable ECC detection.
     * Enable single bit error status capture and ESM notification.
     *  ECC memory writes are enabled. */
    l2ramwREG->RAMCTRL = ((0xA << 0) | (0x1<<4) | (0x1 << 8));

    (*(volatile uint32 *)(0x08000000 )) = 0x8421842184218421;

    /* Force a single bit error */
    uint32 ecc1 = *(volatile uint32 *)(0x08400000) ^ 0x01 ;

    /* Read the corrupted data to generate single bit error */
    eccram_read1 = (*(volatile uint32 *)(0x08000000 ));

    //if((l2ramwREG->RAMERRSTATUS & 0x280000u) == 0x280000u) /* Check for error status

}

/* USER CODE END */

After doing these steps I checked the memory browser. I'm not able to find the update with the mentioned location.i also tried to to fill memory from the memory browser. 

  1. What is the issue here?
  2. What are the configurations to be done to check in the memory browser?
  3. And how can I verify the error injection is successful?

Kindly revert at the earliest possible

  • Hello,

    For 1-bit ECC detected by the CPU it will notify the EPC and eventually go to the ESM GP1.4. After the CPU detects a 1-bit ECC error it signals the EPC along with the corresponding error address. The EPC contains a CAM (content addressable memory) where the error address will be scanned through the CAM to see if there is a match. If there is no match then the 1-bit error address is stored in the CAM and the ESM GP1.4 is set if SERRENA control bits in EPCCNTRL is enabled.

      epcREG1->EPCCNTRL |= 0x0A;

    For 2-bit ECC detected by the CPU it will go to the ESM directly via GP2.3

  • Can you please provide answer for the second part of my question regarding memory browser?

           

    After doing these steps I checked the memory browser. I'm not able to find the update with the mentioned location. I also tried to to fill memory from the memory browser. 

    1. What is the issue here?
    2. What are the configurations to be done to check in the memory browser?
    3. And how can I verify the error injection is successful?
  • Did you define a MPU region for L2RAM ECC memory (starting at 0x08400000)?

  • No it was not defined. How can I define this MPU region for L2RAM ECC memory?

    Is it using MPUREGACR register?

  • You can define it using HALCoGen. TMS570LC43x supports 16 MPU regions. You can select any un-used region for L2RAM ECC.

  • Thank you for the update. One question w.r.t to your above answer

    Do I have to use any of the registers motioned in section 11.4 along with this configuration?

    I can see the register MPUTYPE used to Indicates the number of implemented MPU regions and other few as well related to Enable MPU region. Can you provide the list of registers that I have to use?

  • Can you please provide or mention the document where I can find all the required details w.r.t halogen config as well as the detailed steps to check the RAM ecc functionality. 

  • About MPU, please refer to the ARM Cortex-R5F TRM: https://developer.arm.com/documentation/ddi0460/d/Memory-Protection-Unit?lang=en

    HALCoGen Configuration: Please use the HAL help menu: HalCoGen Help topics and help example 

    RAM ECC: chapter 8 and chapter 12 of TMS570LC43x TRM. For 1-bit or 2-bit ECC error diagnostic test, you can use the method mentioned in the TRM 8.2.6.

    1. Write 64-bit data to a RAM location

    2. program the address to DIAG_Data registers,

    3. program the ECC value with 1-bit error or 2-bit error to DIAG_ECC register,

    4. trigger the diagnostic test, the test will set the error flag.

  • The HALCoGen generates the MPU init function (in HL_sys_mpu.asm). In HALCOGen default MPU setting, only region 1, 2, 3, 4, 5, 6, 7, 16 are used, so you can use region 8 or 9, .. or 15 for RAM ECC memory. 

    If you like to use region 12 for RAM ECC memory, check the "Enable Mpu Region" in "Region 12 Configuration" first, then type the starting address of RAM ECC memory space, and select the memory size, and select the type and permission for this memory space.

    The new MPU configuration code will be generated after the "generate code" is clicked. The _mpuInit_() should be called. 

  • BTW, the _mpuInit_() is called in _c_int00() function: