We are running PTP over lwIP (+FreeRTOS, if that matters), and I observed that when the EMAC clock update mode is set to Fine (TIMSTCTRL:TSFCUPDT=1) the clock (TIMSEC/TIMNANO) halts after a few (4-7) seconds. Starting it in Coarse mode, or setting/clearing TSFCUPDT in the debugger, makes it stop/start immediately (in human time).
I expect that an update would take a longer time in Fine mode, but it seems as though the counter should keep counting. I also tried waiting for a few minutes, re-ordering the TSEN/TSFCUPDT settings, putting something in TIMADD, and setting ADDREGUP, none of which had a visible effect. I also checked the E2E, the MSP432E-series Errata (SLAZ709) and even the TM4C1294 Errata (SPMZ850G) and didn't see a likely suspect.
The code that sets Fine mode came from the SDK [msp432e4if.c, ca. line 400] so I expect that someone somewhere is succeeding with this, but I didn't find a way.
I suppose we can live with Coarse mode for now, but I have a feeling I'm missing something obvious. Has anyone seen this symptom?
