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TMS570LC4357: MibSPI with DMA data transfer stability

Chandra Sekhar
Prodigy 50 points
Part Number: TMS570LC4357

This is with reference to the previous discussion https://e2e.ti.com/support/microcontrollers/other-microcontrollers-group/other/f/other-microcontrollers-forum/995129/tms570lc4357-mibspi-with-dma-buffer-transfer-cs-issue.

The MibSPI and DMA transfer are stable at 15MHz clock frequency with big data buffer (E_COUNT 64 and F_COUNT 4 )

Using update mode as 5 with BTC interrupt to initiate TX.

 with 20MHz clock the frame overlap observed. Please refer the previous discussion for details.

Few questions asked in the previous discussion, which are not yet answered. Request to provide your observations.

1.When the BTC interrupt was hit, I am reconfiguring the DMA channel to trigger TX. May be this is not correct. Please let me know, what is the proper method.

2.To synchronize the TX and RX between both the channels I am using buffer mode as 5 (Wait until TX full). Please note that my communication is between two different controllers, and I need to create mirror image of global data buffer with least possible latency. Shall I need to use different buffer mode for proper sync.

3.What is the highest clock speed can be used practically with MibSPI.

4.I am using motor control FOC in the ETPWM interrupt, which was configured for 25 KHz cycle time. Do this interrupt have any impact on the DMA transfer?

Thanks. Chandra

  • 0
    TI__Guru**** 197016 points

    Hi Chandra,

    1. If you use the same DMA packet configuration, you don't have reconfig it again. The DMA channel  should be re-enabled (HW or SW) is required, and MibSPI DMA channel should be re-enabled too. For example:

       dmaSetChEnable(DMA_CH1, DMA_HW);

       mibspiREG1->DMACTRL[0] |= (1 << 20) | (0 << 16);
       mibspiREG1->DMACTRL[0] |= 0x8000C000;

    2. What is the VCLK in SPI slave? The maximum input SPICLK in slave side is VCLK/2. If SPIENA is not used in slave, 6 vclk delay should be inserted by SPI master between each transfer.

    3. The maximum SPI clock is 25Mbps

    4. DMA transfers data between SRAM and MibSPI RAM, and CPU processes the received data in SRAM. If the ePWM interrupt service routine takes too long time, the DMA transfer may overwrite the data in SRAM which has not been processed by CPU.