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MSP432P401M: Unable to configure Port J.0, J.1, J.2, J.3, J.4, and J.5 pins as GPIOs using TI PinMux tool

rperezti
Genius 12670 points

Part Number: MSP432P401M

The I/O pins associated with HFXT (J2 and J3) and 4-wire JTAG (J4 and J5) can be used as GPIO if those features are not needed in a system. The device H/W fully supports this functionality but the TI PinMux tool on dev.ti.com (SysConfig (1.8.1+1900)) lists these pin configurations as N/A and does not allow the pins to be configured as GPIO.

Can this limitation of SysConfig (1.8.1+1900) be fixed or are there any workarounds available besides manually editing the output files?

  • +1
    TI__Mastermind 49692 points

    Hi Ruben,

    I can confirm what you've observed. Pins PJ.0 to PJ.5, SWDIOTMS and SWCLKTCK are considered "Fixed (N/A)" in SysConfig, similar to other pins such as DVSSx and AVSSx.

    I suspect the reason why is that SysConfig may not know which JTAG interface is used, either SWD or JTAG, so all these related pins are fixed by default. I assume the reason for this limitation is that SysConfig cannot access or read the .ccxml file, which defines the JTAG interface based on the selection made in CCS under the Target Configuration menu.

    I will file a bug to report this although I don't have an estimate on when or if it can be resolved. For now, I would recommend modifying the files based on the JTAG interface selected.

  • +1 in reply to James Evans
    TI__Genius 12670 points

    Thanks James. Note that a similar thing is going on with the two HFXT pins. If a design uses DCO versus HFXT then these pins can be reused as GPIO, but SysConfig doesn't allow that selection.

  • 0 in reply to rperezti
    TI__Mastermind 49692 points

    Hi Ruben,

    Thanks for pointing that out. I updated the bug submission to specifically mention the LFXT/HFXT pins along with the JTAG pins - basically all J.x pins. I would assume it would be easier to fix the clock pins, since a user will choose if a crystal is used or not in SysConfig.