TMS570LC4357: possible to load part of code in cache RAM?

Hi Art,

The CPU fetches the instructions one at a time from the main memory into the registers, then decodes the instruction and executes the instruction. On cache hit, it gets the instruction from cache, but if not (miss), it reads the instruction from main memory and stores it to cache. 

I don't know how to load 32KB block of code into cache at a time. 

Art Mecina said:

Is it possible to load 32ko of code in cache RAM and lock it to get full speed on this part of code only?

Previous investigation in TMS570LC4357: Simulate a lock mechanism for the cache indicates this is not supported.

Hello,

Good day.

What is the pseudo random strategy for cache memory management and why is it impossible for a tool such as aIT from absint to simulate it?

Thanks and regards,

Art

By the way, I might direct our customer to this thread for additional inquiries from his side.

Thanks and regards,

Art

Art Mecina said:

What is the pseudo random strategy for cache memory management and why is it impossible for a tool such as aIT from absint to simulate it?

I haven't used a tool such as aiT, but did notice that a TMS570LC4357 appears as a supported device derivative on aiT for ARM factsheet. The factsheet says:

aiT for ARM statically computes tight bounds for the worst-case execution time (WCET) of tasks in real-time systems. It directly analyzes binary executables and takes the intrinsic cache and pipeline behavior into account.

From the ARM Cortex-R5 documentation I can't see a definition of what the pseudo random strategy is. Guess this is a question for ARM and/or absint as to:

1. Do ARM define what the pseudo random strategy is?
2. How does aIT model the cache to know when a cache line is evicted?