TMS570LS3137: DP83640 Precision PHYTER Communication Problem

Hello,

The  MDIO clock is driven from VCLK3, and the maximum MDIO clock is 2.5MHz. Do you use the MDIO driver generated by HalCoGen? What is MDIO clock frequency used in your test?

Hello, clocks are different in the mdio.h and HalCoGen even I regenerate code and rebuild CCS file.

Configuration in the mdio.h as follows:

/* MDIO input and output frequencies in Hz */
#define MDIO_FREQ_INPUT ((uint32)(VCLK3_FREQ * 1000000.00F))
#define MDIO_FREQ_OUTPUT 1000000U

But in the HalCoGen file I adjusted the VCLK3 Divider to 6 from 1 so VCLK3 clock became 22.857 MHZ

MDIO_CLK=1MHz is used in your test. 

I read PHY ID from Ethernet PHY on HDK:

1. MDIO_CONTROL = 0x4100004F;     //VCLK3=80MHz, MDIO_CLK=1MHz

2. MDIO_USERACCESS0 = 0              // Read Phy Id 1
                                           | ( 1 << 31 ) // [31] Go
                                           | ( 0 << 30 ) // [30] Read
                                           | ( 0 << 29 ) // [29] Ack
                                           | ( 2 << 21 ) // [25-21] PHY register address
                                           | ( 1 << 16 ) // [20-16] PHY address
                                           | ( 0 << 0 ); // [15-0] Data

   while( MDIO_USERACCESS0 & 0x80000000 ); // Wait for Results

   unsigned short value = MDIO_USERACCESS0;

my phy id is:

#define DP83640_PHY_ID                   (0x0007C0F0u)

this is my hw_mdio.h file generated by holcogen for TMS570LS31

/*
* hw_mdio.h
*/

/*
* Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com
*
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the
* distribution.
*
* Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*/

#ifndef _HW_MDIO_H_
#define _HW_MDIO_H_

/* USER CODE BEGIN (0) */
/* USER CODE END */

#ifdef __cplusplus
extern "C" {
#endif

/* USER CODE BEGIN (1) */
/* USER CODE END */

#define MDIO_BASE (0xFCF78900U)

#define MDIO_REVID (0x0U)
#define MDIO_CONTROL (0x4U)
#define MDIO_ALIVE (0x8U)
#define MDIO_LINK (0xCU)
#define MDIO_LINKINTRAW (0x10U)
#define MDIO_LINKINTMASKED (0x14U)
#define MDIO_USERINTRAW (0x20U)
#define MDIO_USERINTMASKED (0x24U)
#define MDIO_USERINTMASKSET (0x28U)
#define MDIO_USERINTMASKCLEAR (0x2CU)
#define MDIO_USERACCESS0 (0x80U)
#define MDIO_USERPHYSEL0 (0x84U)
#define MDIO_USERACCESS1 (0x88U)
#define MDIO_USERPHYSEL1 (0x8CU)

/**************************************************************************\
* Field Definition Macros
\**************************************************************************/

/* REVID */

#define MDIO_REVID_REV (0xFFFFFFFFU)
#define MDIO_REVID_REV_SHIFT (0x00000000U)

/* CONTROL */

#define MDIO_CONTROL_IDLE (0x80000000U)
#define MDIO_CONTROL_IDLE_SHIFT (0x0000001FU)
/*----IDLE Tokens----*/
#define MDIO_CONTROL_IDLE_NO (0x00000000U)
#define MDIO_CONTROL_IDLE_YES (0x00000001U)

#define MDIO_CONTROL_ENABLE (0x40000000U)
#define MDIO_CONTROL_ENABLE_SHIFT (0x0000001EU)

#define MDIO_CONTROL_HIGHEST_USER_CHANNEL (0x1F000000U)
#define MDIO_CONTROL_HIGHEST_USER_CHANNEL_SHIFT (0x00000018U)

#define MDIO_CONTROL_PREAMBLE (0x00100000U)
#define MDIO_CONTROL_PREAMBLE_SHIFT (0x00000014U)
/*----PREAMBLE Tokens----*/

#define MDIO_CONTROL_FAULT (0x00080000U)
#define MDIO_CONTROL_FAULT_SHIFT (0x00000013U)

#define MDIO_CONTROL_FAULTENB (0x00040000U)
#define MDIO_CONTROL_FAULTENB_SHIFT (0x00000012U)
/*----FAULTENB Tokens----*/

#define MDIO_CONTROL_CLKDIV (0x0000FFFFU)
#define MDIO_CONTROL_CLKDIV_SHIFT (0x00000000U)
/*----CLKDIV Tokens----*/

/* ALIVE */

#define MDIO_ALIVE_REGVAL (0xFFFFFFFFU)
#define MDIO_ALIVE_REGVAL_SHIFT (0x00000000U)

/* LINK */

#define MDIO_LINK_REGVAL (0xFFFFFFFFU)
#define MDIO_LINK_REGVAL_SHIFT (0x00000000U)

/* LINKINTRAW */

#define MDIO_LINKINTRAW_USERPHY1 (0x00000002U)
#define MDIO_LINKINTRAW_USERPHY1_SHIFT (0x00000001U)

#define MDIO_LINKINTRAW_USERPHY0 (0x00000001U)
#define MDIO_LINKINTRAW_USERPHY0_SHIFT (0x00000000U)

/* LINKINTMASKED */

#define MDIO_LINKINTMASKED_USERPHY1 (0x00000002U)
#define MDIO_LINKINTMASKED_USERPHY1_SHIFT (0x00000001U)

#define MDIO_LINKINTMASKED_USERPHY0 (0x00000001U)
#define MDIO_LINKINTMASKED_USERPHY0_SHIFT (0x00000000U)

/* USERINTRAW */

#define MDIO_USERINTRAW_USERACCESS1 (0x00000002U)
#define MDIO_USERINTRAW_USERACCESS1_SHIFT (0x00000001U)

#define MDIO_USERINTRAW_USERACCESS0 (0x00000001U)
#define MDIO_USERINTRAW_USERACCESS0_SHIFT (0x00000000U)

/* USERINTMASKED */

#define MDIO_USERINTMASKED_USERACCESS1 (0x00000002U)
#define MDIO_USERINTMASKED_USERACCESS1_SHIFT (0x00000001U)

#define MDIO_USERINTMASKED_USERACCESS0 (0x00000001U)
#define MDIO_USERINTMASKED_USERACCESS0_SHIFT (0x00000000U)

/* USERINTMASKSET */

#define MDIO_USERINTMASKSET_USERACCESS1 (0x00000002U)
#define MDIO_USERINTMASKSET_USERACCESS1_SHIFT (0x00000001U)

#define MDIO_USERINTMASKSET_USERACCESS0 (0x00000001U)
#define MDIO_USERINTMASKSET_USERACCESS0_SHIFT (0x00000000U)

/* USERINTMASKCLEAR */

#define MDIO_USERINTMASKCLEAR_USERACCESS1 (0x00000002U)
#define MDIO_USERINTMASKCLEAR_USERACCESS1_SHIFT (0x00000001U)

#define MDIO_USERINTMASKCLEAR_USERACCESS0 (0x00000001U)
#define MDIO_USERINTMASKCLEAR_USERACCESS0_SHIFT (0x00000000U)

/* USERACCESS0 */

#define MDIO_USERACCESS0_GO (0x80000000U)
#define MDIO_USERACCESS0_GO_SHIFT (0x0000001FU)

#define MDIO_USERACCESS0_WRITE (0x40000000U)
#define MDIO_USERACCESS0_READ (0x00000000U)
#define MDIO_USERACCESS0_WRITE_SHIFT (0x0000001EU)

#define MDIO_USERACCESS0_ACK (0x20000000U)
#define MDIO_USERACCESS0_ACK_SHIFT (0x0000001DU)

#define MDIO_USERACCESS0_REGADR (0x03E00000U)
#define MDIO_USERACCESS0_REGADR_SHIFT (0x00000015U)

#define MDIO_USERACCESS0_PHYADR (0x001F0000U)
#define MDIO_USERACCESS0_PHYADR_SHIFT (0x00000010U)

#define MDIO_USERACCESS0_DATA (0x0000FFFFU)
#define MDIO_USERACCESS0_DATA_SHIFT (0x00000000U)

/* USERPHYSEL0 */

#define MDIO_USERPHYSEL0_LINKSEL (0x00000080U)
#define MDIO_USERPHYSEL0_LINKSEL_SHIFT (0x00000007U)

#define MDIO_USERPHYSEL0_LINKINTENB (0x00000040U)
#define MDIO_USERPHYSEL0_LINKINTENB_SHIFT (0x00000006U)

#define MDIO_USERPHYSEL0_PHYADRMON (0x0000001FU)
#define MDIO_USERPHYSEL0_PHYADRMON_SHIFT (0x00000000U)

/* USERACCESS1 */

#define MDIO_USERACCESS1_GO (0x80000000U)
#define MDIO_USERACCESS1_GO_SHIFT (0x0000001FU)

#define MDIO_USERACCESS1_WRITE (0x40000000U)
#define MDIO_USERACCESS1_WRITE_SHIFT (0x0000001EU)

#define MDIO_USERACCESS1_ACK (0x20000000U)
#define MDIO_USERACCESS1_ACK_SHIFT (0x0000001DU)

#define MDIO_USERACCESS1_REGADR (0x03E00000U)
#define MDIO_USERACCESS1_REGADR_SHIFT (0x00000015U)

#define MDIO_USERACCESS1_PHYADR (0x001F0000U)
#define MDIO_USERACCESS1_PHYADR_SHIFT (0x00000010U)

#define MDIO_USERACCESS1_DATA (0x0000FFFFU)
#define MDIO_USERACCESS1_DATA_SHIFT (0x00000000U)

/* USERPHYSEL1 */

#define MDIO_USERPHYSEL1_LINKSEL (0x00000080U)
#define MDIO_USERPHYSEL1_LINKSEL_SHIFT (0x00000007U)

#define MDIO_USERPHYSEL1_LINKINTENB (0x00000040U)
#define MDIO_USERPHYSEL1_LINKINTENB_SHIFT (0x00000006U)

#define MDIO_USERPHYSEL1_PHYADRMON (0x0000001FU)
#define MDIO_USERPHYSEL1_PHYADRMON_SHIFT (0x00000000U)

/* USER CODE BEGIN (2) */
/* USER CODE END */

#ifdef __cplusplus
}
#endif

#endif

Hi,

Do you enable the MDIO and MDCLK in HalCoGen pinmux config window? Those two signals are not selected when you enable MII or RMII. You have to enable those two signals manually.

Hi,

I already activated them. I stuck at this point.

/* wait for command completion*/
/*SAFETYMCUSW 28 D MR:NA <APPROVED> "Hardware status bit read check" */
while((HWREG(baseAddr + MDIO_USERACCESS0) & MDIO_USERACCESS0_GO) == MDIO_USERACCESS0_GO)
{
} /* Wait */

Hi,

Which hardware board do you use? Is the PHY clocked properly? MII requires 25MHz, and RMII requires 50MHz.

Hi,

Hardware is not validated yet. I double-checked the crystal, and it generates 50 MHz for the RMII connection. Also I see signal at MDIO and MDCLK inputs of PHY.  I also suspect PHY versions are not compatible. 

Do you use TI EVM or your own board?

If you use RMII, the DP83640 RX_DV pin should be pulled HIGH. To use MII mode, the DP83640 RX_DV pin should be pulled LOW.

It is our own board and only designed for RMII. DP83640 RX_DV pin is pulled LOW so I can not use RMII even I configured software for RMII. 

Yes, Since RX_DV=LOW, the MII mode is selected, so you can not use RMII mode. The 50MHz crystal is used for DP83640 PHY, but MII mode requires 25MHz or 2.5MHz for PHY, so MII mode will not work either.

Please correct one of them (RX_DV, or Crystal clock).

1. RX_DV = HIGH, crytal = 50MHZ  --> RMII

2. RX_DV = LOW, crystal = 25MHz (for 100mips) or 2.5MHz (for 10mbps) --> MII