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TMS570LS3137: PBIST

Susan Yang
Genius 9955 points

Part Number: TMS570LS3137

Dear team,

Regarding part of Chapter 7 of the Technical Manual,

1. The RAMT register can be written. What is the function of the written data? What are the functions of DWR, SMS, PLS and RLS in RAMT register? Actual meaning?
2. How to perform failure processing to reduce the value of FSRC and the meaning of the data recorded by FSRDL? Algorithm background patterns?

  • +1
    TI__Guru**** 199216 points

    Hi Susan,

    1. DWR specifies the data width of the RAM to be tested.

        SMS is to select the RAM margins that are supported. This is a discontinued feature and is not supported.

        PLS is pipeline latency select. PBIST supports programmable RAM pipeline latency for big chips. 

        RLS is RAM latency select. PBIST supports multiple RAM latency. PBIST controller sends one access for every N cycles where N is the number of RAM wait states.

    2. FSRDLx contains the failure data. 

  • 0 in reply to QJ Wang
    TI__Genius 9955 points

    Thanks for your reply.

    In the two examples of pbist, the lowest bit of the MSIENA register is set to 1.

    According to the description of Table 2-41, MSIENA seems that the corresponding bit should be enabled according to the configuration corresponding to the memory to be self-tested. Or did I understand it wrong?

  • 0 in reply to Susan Yang
    TI__Guru**** 199216 points

    There is only one PBIST controller. For PBIST test, the bit 0 of MSIENA register is set. 

    For memory initialization, the memory groups are written to MSIENA register.