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RM48L952: RM48L952_SIL3

Ganesh VInayagam
Prodigy 170 points
Part Number: RM48L952
Other Parts Discussed in Thread: HALCOGEN

Hi,

How did you achieved SIL3 in RM48L952,

Please share the SIL3 Achieved Eval Schematics for our reference design purpose.

Also External watchdog is mandatory for the SIL3 achievement?.

Thanks and Regards,

Ganesh V  

  • 0
    TI__Guru**** 197306 points

    Hi Ganesh,

    From an MCU standpoint, there is no problem to use RM4x in SIL3 designs. RM48x is certified suitable for use in SIL3 systems by TUEV SUED. There are specific requirements associated with safety SW development that you would need to comply with. These requirements are specified in the applicable standards and usually cover such items as software test, metrics, coding standards, compiler certification/qualification, etc. TI offers a Compiler Qualification Kit (CQK) and Certification Support Packages (CSPs) for software that is available for use with Hercules (Halcogen and/or SafeTI Diagnostic Library). 

    For achieving SIL-3, an external watchdog is mandatory, regardless of the capability of the on-chip watchdog. This is mainly due to common-cause dependencies such as clock sources, etc.

    An external supply supervisor is also required. The Hercules device has an on-chip voltage monitor whose primary function is to allow the I/O and core supplies to be powered up/down in any sequence. TPS65381 PMIC is indeed designed to work with Hercules MCUs, and meets the requirements of both a supply supervisor and a CPU watchdog.

    We don't have certified SIL-3 EVM board. 

  • 0 in reply to QJ Wang
    Prodigy 170 points

    Hi, 

    Thank you for your input,

    DO we need to take any other design control for SIL 3 achieve.

     

    Whether this RM48 device has the Hardware secure boot  features ?

    Also is there any other controller which has SIL3 controller also Hardware secure boot features please suggest.

  • 0 in reply to Ganesh VInayagam
    TI__Guru**** 197306 points

    Hello Ganesh,

    The SIL is determined based on a number of quantitative and qualitative factors such as development process and safety life cycle management. For example, the safety lifecycle includes a hazard and risk assessment phase, in which all significant hazardous events have to be identified and analyzed, then assessed for determining the level of risk reduction required to achieve a target level of risk. For RM48x, please refer to the diagnostic mechanism listed in safety manual.

     RM48 doesn't support secure boot.

  • 0 in reply to QJ Wang
    Prodigy 170 points

    Hi Wang,

    Thanks for your reply,

    How to handle the un  used pin in RM48 controller,

    We can left open or need to connect Pull down for SIL-3.

    Thanks and Regards,

    Ganesh V

  • 0 in reply to Ganesh VInayagam
    Prodigy 170 points

    Hi Wang,

    Thanks for your reply,

    How to connect the ARM 10 pin JAT connection.

    XDS100V2  help with connection details.

    Can we use FTSH-105-01-L-DV-K for JTAG connector  for RM48 device .  

  • 0 in reply to Ganesh VInayagam
    TI__Guru**** 197306 points

    Hello Ganesh,

    For the unused GIO pins, it's ok to leave them UC.

    ARM 10-pin header doesn't include JTAG RTCK (return clock) which allows the JTAG emulator to support adaptive clocking.

    Please check the JTAG headers used on must TI EVM boards.

    https://software-dl.ti.com/ccs/esd/documents/xdsdebugprobes/emu_jtag_connectors.html

    There are more information regarding xds100:

    https://software-dl.ti.com/ccs/esd/documents/xdsdebugprobes/emu_xds100.html

    and xds110:

    https://software-dl.ti.com/ccs/esd/documents/xdsdebugprobes/emu_xds110.html