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Nested Interrupts Implementation

Tony Morrell
Genius 4130 points

Hi,

My questions relate to nested interrupts, particularly FIQs.

From previous post discussions I see that it is possible to achieve nested interrupts for IRQs by re-enabling IRQ from within the ISR to be interruptable (http://e2e.ti.com/support/microcontrollers/tms570/f/312/p/59793/213613.aspx#213613). I am trying to achieve the same result for FIQs but without success so far. I think I am primarily stuck at the context save. Even though it looks as though the FIQs push registers onto the stack at start and pop them off at finish, I think this might not be enough, do these registers encompass the entire required context?

I have two FIQs, one higher priority than the other, so I want the higher priority FIQ to interrupt the lower priority FIQ, and then on completion, for the lower priority FIQ to continue.

Is it possible to nest FIQs as has been suggested for IRQs?

If so, does anybody have any examples describing how to perform context saving, including the general purpose registers?

Regards, Tony.

  • 0
    TI__Expert 4580 points

    Hello:

    Were you able to solve your nested FIQs issue?

    Regards,

    Enrique

  • 0 in reply to Enrique Lizarraga
    TI__Mastermind 22375 points

    Tony,

    The main difference between IRQ and FIQ is the fact that the CPU has a set of dedicated general purpose registers when you enter FIQ.
    These registers are R8 to R12.
    Usually the code generation tools uses these registers when a function is defined as FIQ routine.
    In this case, there is no need to push in the stack the registers used in your FIQ service routine. (Fast interrupt)

    Also, the CPU will automatically disable FIQ as soon as it enters in FIQ mode to avoid nested FIQ.

    Nevertheless, it is possible within the FIQ service routine to re-enable FIQ. In this case, it will be necessary to push in the stack all your context.

     

    Note: On TMS570, FIQ are used as NMI. Once the F bit is cleared in the CPSR, it can't be set anymore. Only a reset or when the CPU enters FIQ/NMI can set this bit.

    Please let me know if this clarify your question.

    Best Regards,

    Jean-Marc