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TMS570LC4357: To enable interrupt for ESM

Aporva Srivastava
Prodigy 30 points
Part Number: TMS570LC4357

Hi team,
We are using TMS570LC4357 processor for our project. Our requirement is to enable Single Bit RAM , Multi Bit RAM, Single Bit Flash, Multi Bit Flash and CPU compare error while running the software and generate the ESM interrupt for all these faults.

We have enabled ESM interrupt by setting IESR1 and IESR4 as below.
esm_base[IESR1] = 0x04000040UL;
esm_base[IESR4] = 0x80080UL;

Currently, when we are trying to simulate these faults, it is generating the exception (data abort) and respective error bit is not getting set in ESMSR1 or ESMSR1 register respectively.

Please let us know if more configuration need to be done for it and any preferable approach to simulate these faults.

  • 0
    TI__Guru**** 196526 points

    How do you generate those error? 

    esm_base[IESR4] = 0x80080UL; --> channel 39 is for Power domain selftest error, and channel 51 is DCAN4 ECC error 

  • 0 in reply to QJ Wang
    Prodigy 30 points

    For single bit RAM and FLASH, since interrupt is enabled in IESR1 register but still we are not able to generate ESM interrupt. For multi bit flash and RAM error and CPU compare error , I am not able to find the register to enable the interrupt. (For group 2).

    Please let us know how to enable the interrupt for ESM and method to test it.

  • 0 in reply to Aporva Srivastava
    TI__Guru**** 196526 points

    Hi,

    TMS570LC43x device has an Error Profiling Controller module (EPC). The main idea of EPC is to enable the system to tolerate a certain amount of ECC correctable errors on the same address repeatedly in the memory system. If a correctable ECC error is generated on a repeating address, the EPC will not raise an error to ESM module.

    For correctable faults, the error handling depends on the following conditions:
       – if the incoming address is already in the 32-entry CAM, discard the fail. No error generated to ESM.
       – if the address is not in the CAM list, and the CAM has empty entries, add the address into the CAM list. In addition, raise the error signal to the ESM group 1 if enabled. -- ESM 1.4
       – if the address is not in the CAM list, and the CAM has no empty entries, always raise the error signal to the ESM group 1. -- ESM1.4

    For uncorrectable faults, capture the address and assert error signal to the ESM group 2. -- ESM2.21

    If the interrupt for ESM1.4 is enabled, the interrupt should be generated if 1-bit ECC occurs and the address is not in the CAM list. The interrupt is always generated for 2-bit ECC error (ESM2.21).