Dear Champs,
My customer is implement deep sleep mode in RM46L852 by referring TRM, and it seems they can enter Deep sleep mode successfully, but failed to wake-up using DCAN.
To enable WUBA bit in the DCAN Ctrl register, they added below code, but they failed to wake-up by CAN messages.
canREG1->CTL = (uint32)0x00000000U
| (uint32)0x00000000U
| (uint32)((uint32)0x00000005U << 10U)
| (uint32)((uint32)0x00000001U << 25U) // WUBA enable
| (uint32)0x00020043U;
Their code for Deep sleep is as below. Could you please check below code to wake-up through DCAN?
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uint32_t sleep_clk; canREG1->CTL |= (((uint32_t) 1U << 2 ) /* Enable Status Interrupts*/ | (uint32_t)((uint32_t)0x1U << 25U)); canREG1->ES |= ((uint32_t)0x1 << 9); canREG1->CTL &= ~(uint32)(0x00000041U);/*Clear Init Bit*/ pcrREG->PSPWRDWNSET1 &= ~(uint32)(0x00000003U); /*Power Down DCAN1*/
vimREG->WAKEMASKSET0 =0xFFFFFFFF; vimREG->WAKEMASKSET1 =0xFFFFFFFF; vimREG->WAKEMASKSET2 = 0xFFFFFFFF; vimREG->WAKEMASKSET3 = 0xFFFFFFFF; vimREG->WAKEMASKCLR0 = 0xFFFFFFFF; vimREG->WAKEMASKCLR1 = 0xFFFFFFFF; vimREG->WAKEMASKSET0 = 1U << 16U | 1U << 29U;
_enable_IRQ();
/** Setup Flash Banck Access Control **/ //flashWREG->FBAC = (0x0F << 8) | (0x0F); flashWREG->FBAC = 0x00000000U |(uint32)((uint32)15U<< 8U) //BAGP |(uint32)((uint32)15U); //VREADST
/** - Setup flash bank power modes */ flashWREG->FBFALLBACK = 0x00000000U | (uint32)((uint32)SYS_SLEEP << 14U) /* BANK 7 */ | (uint32)((uint32)SYS_SLEEP << 2U) /* BANK 1 */ | (uint32)((uint32)SYS_SLEEP << 0U); /* BANK 0 */
// Flash pump - all pump circuits disabled flashWREG->FPAC1 = flashWREG->FPAC1 & ~(0x1U); flashWREG->FPAC2 = 0x0;
/** - Setup GCLK, HCLK and VCLK clock source for normal operation, power down mode and after wakeup */ systemREG1->GHVSRC = (uint32)((uint32)SYS_LPO_HIGH << 24U) | (uint32)((uint32)SYS_LPO_HIGH << 16U) | (uint32)((uint32)SYS_PLL1 << 0U);
/** - Setup asynchronous peripheral clock sources for AVCLK1 and AVCLK2 */ systemREG1->VCLKASRC = (uint32)((uint32)SYS_LPO_HIGH << 8U) | (uint32)((uint32)SYS_LPO_HIGH << 0U);
sleep_clk = (uint32)((uint32)1U << 0U) |(uint32)((uint32)0U << 1U) |(uint32)((uint32)1U << 3U) |(uint32)((uint32)1U << 4U) |(uint32)((uint32)0U << 5U) |(uint32)((uint32)1U << 6U) |(uint32)((uint32)1U << 7U);
systemREG1->CSDIS = sleep_clk;
while((systemREG1->CSDIS & sleep_clk) != sleep_clk) { /* Wait */ }
systemREG1->CDDIS = 0x1 //RTICLK is enabled for wakeup | (uint32)((uint32)1U << 0U ) /* GCLKOFF */ | (uint32)((uint32)0U << 1U ) /* HCLK OFF */ | (uint32)((uint32)0U << 2U ) /* VCLKP OFF */ | (uint32)((uint32)1U << 3U ) /* VCLK2 OFF */ | (uint32)((uint32)0U << 4U ) /* AVCLK 1 OFF */ | (uint32)((uint32)1U << 5U ) /* AVCLK 2 OFF */ | (uint32)((uint32)1U << 8U ) /* VCLK3 OFF */ | (uint32)((uint32)1U << 9U ) /* VCLK4 OFF */ | (uint32)((uint32)1U << 10U) /* AVCLK 3 OFF */ | (uint32)((uint32)1U << 11U); /* AVCLK 4 OFF */
asm( " NOP"); asm( " NOP"); asm( " NOP"); asm( " WFI"); asm( " NOP"); asm( " NOP"); asm( " NOP");
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Thanks and Best Regards,
SI.
