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TMS570LC4357: Will a reset of nERROR be possible while there is fault condition signalled to the ESM?

Part Number: TMS570LC4357

Hi experts,

My understanding of the ESM - nERROR  dependency was that the nERROR-Pin is always in LOW state, when there is an error bit set in one of the ESM registers. Which would mean that the nERROR pin can not be reset while the Error in the ESM is not cleared.

But when looking at the documentation again, Figure 16-7 in the Techhnical reference Manual suggests otherwise:

For clarification I added the state of the ESM 2.19 bit to Figure 16-7.

(Q1) Is it possible to reset the nERROR Pin although an error like ESM 2.19 is still present und not cleared?

Thank you and best regards,
Max

  • Hi Max,

    Your understanding is correct. The nERROR is a active low pin. Once an error is detected, the ESM drives the nERROR pin to LOW. If no nERROR in reset is request, the nERROR pin will output LOW until power on reset is applied.

    nERROR RESET request:

    1. Write 0x5 to ESMEKR register

    2. Write 0x0 to ESMEKR register

  • Hi QJ,

    Thank you for your fast reply.

    What  I am wondering is, could doing an error forcing test like CPU8 which would trigger ESM 1.2 and the nERROR Pin (if so configured) leed to a real error not beeing detected? Because the nERROR gets trriggered by this Test we would need to reset the pin with a reset request immediatly.

    What I am worried about is that another ESM Error that is signaled after the reset request would leed to nERROR beeing reset despite there beeing an error present.

    Is this possible?

  • 1. The CCM-R5F error forcing mode forces the compare mismatch to actually assert the compare error output signal. This ensures that a fault in the path between CCM-R5F and ESM is detected. The error forcing mode takes one cycle to complete.

    During the one cycle required by the error forcing test, the CPU output signals are not compared. So you are correct, the real error may not be detected.  

    2. The ESM error after the reset request drives the nERROR pin LOW, and the nERROR pin becomes HIGH immediately after Low-Time Counter expires.

  • Hi QJ,

    Thank you for the clarification.  This basicly means, that it is possible for an error beeing present, without nERROR = LOW, as show in the attached image.

    Is there a way to prevent the nERROR reset, when there is an error present in the ESM?

    Thank you and best regards,
    Max

  • Hi Max,

    The nERROR reset request is done by writing an appropriate key (0x5) to the key register (ESMEKR) during the ERROR pin low time. Clearing the ESM status register doesn't reset the nERROR.

    If you don't write 0x5 to ESKEKR, no ERROR pin reset is requested. The nERROR pin continues outputting low until power on reset occurs.

  • Hi QJ,

    I understand that the ESM just sets the nERROR = LOW and for a reset I have to request a nERROR resett hrough ESKEKR. What I am concerned about is that after the request is set, another error could occur. In the image I posted that would be ESM 3.9.

    In that case, after the specified LOW-time of nERROR ESM 3.9 would still be set, but nERROR would be HIGH.
    Is my understanding correct?

  • The nERROR pin will keep LOW. Writing 0x5 to ESKEKR during nERROR=LOW does not impact the following error.

    If you want to reset nERROR, you need to write 0x5 to ESKEKR after ESM3.9 is set.

  • Hi QJ,

    Thank you for the clarification. So the behaviour in the image I posted is incorrect and the correct behaviour would be the following?

    Thank you and best regards,
    Max

  • Max,

    Yes, you are correct.