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TMS570LS1227: MIBSPI : trigger frequency of internal trigger

v01d
Expert 2025 points
Part Number: TMS570LS1227

I'm having difficulty figuring out how to use the internal MIBSPI trigger as source.  

I have the SPI format (format 0) configured as 1000 KHz, and  I'm setting the tick counter to the max - 0xffff.  I'm configuring to trigger only at rising edge. 

At this rate - SPICLK of the format 0, which is 1000KHz - I expect the trigger to go at approx  every  ~65 ms  * 2 = ~130 ms (counter reload rising, reload falling, etc .. ).

But what I get is seems interrupt as-fast as possible, or it's ending as fast as can, and I have to set buffer mode 6 = Wait for Rx empty to just keep up not to overwrite reads.

If, I change the trigger source to say, external GIOA7 - which is mapped to the user button the 1227 HDK kit - then I get expected behavior, only one send/receive when I press the button. 

I'm out of ideas atm.. 

  • 0
    TI__Guru**** 197036 points

    Hello.

    What is the value of TICKCNT register? Is SPI clock of FMT0 9format 0) is selected as the clock source of tick counter.

    If tick counter is enabled, and clock source and tock value are programmed properly, the MibSPI TG transfer should be triggered at the trigger event.

  • 0 in reply to QJ Wang
    Expert 2025 points

    Hello , thank you for coming to the Rescue as usual.

    Well the value of the TICKCNT is as I describe above, basically has 0xffff in first 16 bits, and then bit 31 is set to enable it , so I do:

    mibspiREG1->TICKCNT  = 0xC000ffff;

    Bit 30 I set to force counter re-load, which sholdn't be necc. when you enable the counter.   The TICKCNT always reads as 0x8000ffff, from debugger.  I cannot verify any other way that the internal tick counter actually ticks , from registers - or can I ?

  • 0 in reply to QJ Wang
    Expert 2025 points

    It appears I was looking at this wrong.  I was comparing times  from break point in ISR to ISR and looking at the value of my RTI counter, to check times.

    But, it seems, the internal SPI counter / trigger or SPICLK which drives it is not stopped when you break in debugger - is that so ? 

    Now I connected protocol analyzer, and the SPI reads are triggered exact per the trigger setup.

    Is there some register setting to tell SPI internal counter to stop if CPU is in debug break?

  • +1 in reply to v01d
    TI__Guru**** 197036 points

    No, the tick counter doesn't stop counting in debug mode.