TMS570LS0432: Arm-based microcontrollers forum

Ivan Liu Zhu

Part Number: TMS570LS0432

Hi,

I would like to understand better how to assert properly the nPORRST pin:

To activate the nPORRST, it must be pulled down to gnd. What would be the nominal voltage for the Pull-up? Vccio voltage?
From timing perspective, nPORRST must be active at least 1ms, until both Vccio and Vcc reach Vccporh and Vccioporh voltages. Is this correct?
From timing perspective, it is shown in the figure 6-1 of the datasheet that nPORRST must be active low before Vcc or Vccio goes below the thresholds Vccporh and Vccioporh. Is this indicating that the voltage of the power lines go low after nPORRST is asserted or does this indicate that the reset needs to be activated before there is an undervoltage?

The idea would be to supply the uC with 2 LDOs, and we would like to implement some comparators that monitor Vcc and Vccio voltages. In case of out of the recommended range, they would trigger the nPORRST. Do you have a similar application diagram?

Any other consideration required to implement correctly the reset?

Thank you in advance.

over 4 years ago

0 QJ Wang over 4 years ago

TI__Guru**** 196246 points

Hello Ivan,

1. Vih is the same as for the other pins (2V up to Vccio+0.3). Vil for nPORRST is described in section 6.3 on nPORRST electrical and timing requirements. The nPORRST should be externally pulled up to VCCIO via a resistor for example 2.2kohms.

2. The nPORRST must be active at least 1ms after Vcc > Vccporh and Vccio > Vccioporh.

3. Yes. The picture 6.1 says that nPORRST must be driven 2us before core supply drops below 1.14V.

Most system designers meet this requirement by tuning the core supply up (e.g. 1.26V nominal instead of 1.2V), and setting the low-threshold higher than 1.14V.

0 Ivan Liu Zhu over 4 years ago in reply to QJ Wang

Prodigy 150 points

Thank you for the support.

What would be the effect in the microcontroller if the nPORRST is triggered after the core drops below 1.14? The idea would be to use a voltage comparator, but it normally triggers more in the 50uS range.
What kind of resets are we trying to address here? From Figure 6-1 I can see two scenarios:
- Short voltage drop in Vcc (1.2V). Aren't these covered by the decoupling capacitors?
- Power down: why would it be necessary to trigger the reset 2us before? Wouldn't it be enough to trigger it after it is detected, no matter what the timing?

Thanks.

0 QJ Wang over 4 years ago in reply to Ivan Liu Zhu

TI__Guru**** 196246 points

The 2us requirement comes from the maximum delay of the glitch filter on the nPORRST pin. The requirement to assert nPORRST before Vcc drops below 1.14V is to make sure that reset is asserted before the core logic can fail. The real concern is that while programming or erasing flash that the high voltage from the flash pump is discharged before the core logic fails.

As mentioned in my previous post, setting the low-threshold higher than 1.14V is a solution.

The decoupling capacitors or bypass capacitors between Vcc pins and GND provide high transient currents and reduces power ripples.