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TMS570LC4357: HalCoGen PLLxDiv blocks don't change the source

jimj2713
Expert 2375 points
Part Number: TMS570LC4357
Other Parts Discussed in Thread: HALCOGEN

I did not see a HalCoGen E2E group, so hopefully this is the correct forum. In HalCoGen (04.07.01), in the TMS550LC4357ZWT tab and PLL page, the 2 divider-selection blocks for each PLL ("PLL 1 Div" and "PLL 2 Div") numeric selections don't change the PLLCTL registers. As I interpret the TRM, these 2 numeric selections ought to change these 2 lines of code:

systemREG1->PLLCTL1 = (uint32)0x80000000U
| (uint32)0x20000000U
| (uint32)((uint32)0x1FU << 24U)

and

systemREG2->PLLCTL3 = (uint32)((uint32)(1U - 1U) << 29U)
| (uint32)((uint32)0x1FU << 24U)

Yet no matter what is selected in the PLL1Div and PLL2Div, the value shifted-up 24 is always 0x1F.

Please check on your HalCoGen.

Thanks,

Jim

  • 0
    TI__Guru**** 197126 points

    Hi Jim,

    The PLLCTL1 and PLLCTL3 are updated in mapClocks() with the new PLLx divider:

    /* Now the PLLs are locked and the PLL outputs can be sped up */
    /* The R-divider was programmed to be 0xF. Now this divider is changed to programmed value */
    systemREG1->PLLCTL1 = (systemREG1->PLLCTL1 & 0xE0FFFFFFU) | (uint32)((uint32)(4U - 1U) << 24U);
    /*SAFETYMCUSW 134 S MR:12.2 <APPROVED> " Clear and write to the volatile register " */
    systemREG2->PLLCTL3 = (systemREG2->PLLCTL3 & 0xE0FFFFFFU) | (uint32)((uint32)(1U - 1U) << 24U);