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TM4C129XNCZAD: UART TX Interrupt not functioning as expected

Strahinja Jacimovic
Prodigy 10 points

Part Number: TM4C129XNCZAD

Hello,

While working on a project I encountered an issue.

I noticed the UART interrupt doesn't really behave as described in the datasheet.

Mainly, I expected the interrupt to be triggered once TX Fifo is empty, but it triggers only when data is written into the data register.

This seems to be a known issue as mentioned in the following discussion:
https://e2e.ti.com/support/microcontrollers/arm-based-microcontrollers-group/arm-based-microcontrollers/f/arm-based-microcontrollers-forum/603001/tm4c129encpdt-uart-transmit-interrupt-not-being-triggered

Has this issue perhaps been fixed on newer versions of the sillicon or is this an issue on all sillicon revisions?

Also, is there perhaps another way for the TX interrupt to be triggered which doesn't include writing into the data register?
(Maybe I missed something obvious)

Thanks in advance.

  • 0
    TI__Guru*** 135355 points

    Hello Strahinja,

    There is not a newer revision of the device since that post was discussed and the only revision available is revision 3.

    I think the information in that thread is as detailed of an analysis of the situation as you will find and the datasheet is quite clear about this:

    ■ If the FIFOs are enabled and the transmit FIFO progresses through the programmed trigger

    level, the TXRIS bit is set. The transmit interrupt is based on a transition through level, therefore

    the FIFO must be written past the programmed trigger level otherwise no further transmit interrupts

    will be generated. The transmit interrupt is cleared by writing data to the transmit FIFO until it

    becomes greater than the trigger level, or by clearing the interrupt by writing a 1 to the TXIC bit.

    Best Regards,

    Ralph Jacobi